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STLC5411
2B1Q U INTERFACE DEVICE
GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE HCMOS3A SGS-THOMSON ADVANCED 1.2m DOUBLE-METAL CMOS PROCESS
PLCC44
TRANSMISSION FEATURES 160 KBIT/S FULL DUPLEX TRANSCEIVER 2B1Q LINE CODING WITH SCRAMBLER/DESCRAMBLER 18KFT (5.5KM) ON 26AWG/24AWG TWISTED PAIR CABLES SUPPORTS BRIDGE TAPS, SPLICES AND MIXED GAUGES >70DB ADAPTIVE ECHO-CANCELLATION ON CHIP HYBRID CIRCUIT DECISION FEEDBACK EQUALIZATION ON CHIP ANALOG VCO SYSTEM DIRECT CONNECTION TO SMALL LINE TRANSFORMER SYSTEM FEATURES ACTIVATION/DEACTIVATION CONTROLLER ON CHIP CRC CALCULATION AND VERIFICATION INCLUDING TWO PROGRAMMABLE BLOCK ERROR COUNTERS EOC CHANNEL AND OVERHEAD-BITS TRANSMISSION WITH AUTOMATIC MESSAGE CHECKING GCI AND MW/DSI MODULE INTERFACES COMPATIBLE DIGITAL LOOPBACKS COMPLETE (2B+D) ANALOG LOOPBACK IN LT ELASTIC DATA BUFFERS AND BACKPLANE CLOCK DE-JITTERIZER AUTOMODE NT1 AND REPEATER "U ACTIVATION ONLY" IN NT1 IDENTIFICATION CODE AS PER GCI STANDARD
November 1996
ORDERING NUMBER: STLC5411FN
Plastic DIP28 ORDERING NUMBER: STLC5411P
EASILY INTERFACEABLE WITH ST5451 (HDLC & GCI CONTROLLER), ST5421 SIDGCI TRANSCEIVER AND ANY OTHER GCI, IDL or TDM COMPATIBLE DEVICES
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STLC5411
INDEX DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W/DSI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line coding and frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elastic buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4 channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spare M5 and M6 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC calculation checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 6 14 14 14 14 14 14 15 18 18 18 22 23 24 24 24 25 25 25 25 26 26 26
Maintenance functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Identification code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 General purpose I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Test functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Turning on and off the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line activation request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power up control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation deactivation sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case of restricted activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset of activation / deactivation state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quiet mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 34 34 35 35 35 35 35 35 35 35 36
Command/Indication (C/I) codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Internal register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Line interface circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53
APPENDIX A: STATE MATRIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 APPENDIX B: ELECTRICAL PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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STLC5411
PIN CONNECTIONS (Top view)
PLCC44 MICROWIRE MODE
PLCC44 GCI MODE
DIP28 MICROWIRE MODE
DIP28 GCI MODE
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STLC5411
Figure 1: Block Diagram.
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STLC5411
GENERAL DESCRIPTION STLC5411 is a complete monolithic transceiver for ISDN Basic access data transmission on twisted pair subscriber loops typical of public switched telephone networks. The device is fully compatible with both ANSI T1.601-1988 U.S. and CSE (C32-11) French specifications. It is intended also to comply with ETSI specification both in term of transmission performances and requested features. The equivalent of 160 kbit/s full-duplex transmission on a single twisted pair is provided, according to the formats defined in the a.m. spec. Frames include two B channels, each of 64 kbit/s, one D channel of 16 kbit/s plus an additional 4 kbit/s M channel for loop maintenance and other user functions. 12 kbit/s bandwidth is reserved for framing. 2B1Q Line coding is used, where pairs of bits are coded into one of 4 quantum levels. This technique results in a low frequency spectrum (160 kbit/s turn into 80 kband), thereby reducing both line attenuation and crosstalk and achieving long range with low Bit Error Rates. The system is designed to operate on standard types of cable pairs including mixed gauges (26 AWG, 24 AWG and 22 AWG) including the 15 loops configuration specified by ANSI. Good noise margins are achieved even when bridged taps are present. On 26 AWG cable, the transmission range is in excess of 5.5 km (18 kft) in presence of crosstalk and noise as specified by ANSI standard. STLC5411 is designed to operate with Bit Error Rate near-end Crosstalk (NEXT) as specified in european ETSI recommendation. To meet these very demanding specifications, the device includes two Digital Signal Processors, one configured as an adaptive Echo-Canceller to cancel the near end echoes resulting from the transmit/receive hybrid interface, the other as an adaptive line equalizer. A Digital Phase-Locked Loop (DPLL) timing recovery circuit is also included that provides in NT modes a 15.36 MHz synchronized clock to the rest of the system. Scrambling and descrambling are performed as specified in the US and French specifications. On the system side, STLC5411 can be linked to two bus configuration simply by pin MW bias. MICROWIRE(W/DSI) mode (MWpin = 5V): 144 kbit/s 2B+D basic access data is transferred on a multiplex Digital System Interface with 4 different interface formats (see fig. 2 and 3) providing maximum flexibility with a limited pin count (BCLK, Bx, Br, FSa, FSb). Three pre-defined 2B+D formats plus an internal time slot assigner allows direct connection of the UID to the most common multiplexed digital interfaces (TDM/IDL). Bit and Frame Synchronisation signals are inputs or outputs depending on the configuration selected. Data buffers allow any phase between the line and the digital interface. That permits building of slave-slave configurations e.g. in NT12 trunkcards. It is possible to separate the D from the B channels and to transfer it on a separate digital interface (Dx, Dr) using the same bit and frame clocks as for the B channels or in a continuous mode using an internally generated 16 kHz bit clock output (DCLK). All the Control, Status and Interrupt registers are handled via a control channel on a separate serial interface MICROWIRE compatible (CI, CO, CS, CCLK, INT) supported by a number of microcontroller including the MCU families from SGSTHOMSON GCI mode (MWpin = 0V). Control/maintenance channels are multiplexed with 2B+D basic access data in a GCI compatible interface format (see fig. 4a) requiring only 4 pins (BCLK, Bx, Br, FSa). On chip GCI channel assignement allows to multiplex on the same bus up to 8 GCI channels, each supporting data and controls of one device. Bit and Frame Synchronisation signals can be inputs or ouputs depending on the configuration selected. Data buffers, again, allow to have any phase between the line interface and the digital interface. Through the M channel and its protocol allowing to check both direction exchanges, internal registers can be configured, the EOC channel and the Overhead-bits can be monitored. Associated to the M channel, there are A and E channels for enabling the exchanged messages and to check the flow control. The C/I channel allows the primitive exchanges following the standard protocol. In both mode (W and GCI) CRC is calculated and checked in both directions internally. In LT mode, the transmit superframe can be synchronized by an external signal (SFSx) or be self running. In NT mode, the SFSx is always output synchronized by the transmit superframe. Line side or Digital Interface side loopbacks can be selected for each B1, B2 or D channel independently without restriction in transparent or in non-transparent mode. A transparent complete analog loopback allowing the test of the transmission path is also selectable. Activation and deactivation procedures, which are automatically processed by UID, require only the exchange of simple commands as Activation Request, Deactivation Request, Activation Indication. Cold and Warm start up procedures are operated automatically without any special instruction. Four programmable I/Os are provided in GCI for external device control.
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STLC5411
PIN FUNCTIONS (no Specific Microwire / GCI Mode) Note: all pin number are referred to Plastic DIP28 package.
Pin 1, 4 Name LO+, LOIn/Out Out, Out Description Transmit 2B1Q signal differential outputs to the line transformer. When used with an appropriate 1:1.5 step-up transformer and the proper line interface circuit the line signal conforms to the output specifications in ANSI standard with a nominal pulse amplitude of 2.5 Volts. Receive 2B1Q signal differential inputs from the line transformer. Positive power supply input for the analog and digital sections, which must be +5 Volts +/-5% and must be directly connected together. Negative power supply pins, which must be connected together close to the device. All digital and analog signals are referred to these pins, which are normally at the system Ground. (LT configuration only) This pin is an open drain output normally in the high impedance state which pulls low when B1 and B2 time-slots are active. It can be used to enable the Tristate control of a backplane line-driver. (NT configuration only) 15.36 MHz clock output which is frequency locked to the received line signal active as soon as UID is powered up except in NT1 Auto configuration (active only if S line activation is requested) The output of the crystal oscillator, which should be connected to one end of the crystal, if used. Otherwise, this pin must be left not connected. The master clock input, which requires either a parallel resonance crystal to be tied between this pin and XTAL2, or a logic level clock input from a stable source. This clock does not need to be synchronized to the digital interface clocks (FSa, BCLK).Crystal specifications: 15.36 MHz +/-50ppm parallel resonant; Rs 20 ohms; load with 33pF to GND each side. MICROWIRE selection: When set high, MICROWIRE control interface is selected. When set low, GCI interface is selected.
2, 3 5, 8 24, 9 23
LI+, LIVCCA, VCCD GNDA,GNDD1 GNDD2
In, In In, In In, In In
10
TSRb
Out
SCLK
Out
20 21
XTAL2 XTAL1
Out In
28
MW
In
PIN FUNCTIONS (specific Micro Wire mode)
Pin 6 Name FSa In/Out In Out Description Input or Output depending of the CMS bit in CR1 register, FSa is a 8 KHz clock which indicates the start of the frame on Bx when FSa is input, or Bx and Br when FSa is output. Input or Output, the location of FSa relative to the frame on Bx or Bx and Br depens of DDM bit in CR1 register, also the selected format. Input or Output depending of the CMS bit in CR1 register, FSb is a 8 KHz clock which indicates the start of the frame on Br when it is an input. When it is an output, FSb is a 8 KHz pulse conforming with the selected format and always indicating the second 64Kbit/sec channel of the frame on Br. Input or Output, the location of FSb relative to the frame on Br depends of DDM bit in CR1 register, also the selected format. 2B+D datas tristate output. Datas received from the line are shifted out on the rising edge (at the BCLK frequency or the half BCLK frequency if format 4 is selected) during the assigned time slot. Br is in high impedance state outside the assigned time slot and during the assigned time slot of the channel if it is disabled. When D channel port is enabled, only B1 B2 are on Br.
7
FSb
In Out
11
Br
Out
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STLC5411
PIN FUNCTIONS (specific Micro Wire mode)
Pin 12 Name BCLK In/Out In Out Description Bit clock input or output depending of the CMS bit in CMR register. When BCLK is an input, its frequency may be any multiple of 8 KHz from 256 KHz to 4096 KHz in formats 1, 2, 3; 512 KHz to 6176 KHz in format 4. When BCLK is an output, its frequency is 256 KHz, 512 KHz, 1536 KHz, 2048 KHz or 2560 KHz depending of the selection in CR1 register. In this case, BCLK is locked to the recovered clock received from the line. Input or Output BCLK is synchronous with FSa/FSb. Datas are shifted in and out (on Bx and Br) at the BCLK frequency in formats 1, 2, 3. In format 4 datas are shifted out at half the BCLK frequency. 2B+D input. Basic access data to transmit to the line is shifted in on the falling edges (at the BCLK frequency or the half BCLK frequency if format 4 is selected) during the assigned time-slots. When D channel port is enabled, only B1 & B2 sampled on Bx. D channel clock output when the D channel port is enabled in continuous mode. Datas are shifted in and out (on Dx and Dr) at 16 KHz on the falling and rising edges of DCLK respectively. In master mode, DCLK is synchronous with BCLK. D channel data output when the D channel port is enabled. D channel data is shifted out from the UID on this pin in 2 selectable modes: in TDM mode data is shifted out at the BCLK frequency (or half BCLK frequency in format 4) on the ridsing edges when the assigned time slot is active. In continuous mode data is shifted out at the DCLK frequency on the rising edge continuously. D channel data input when the D channel port is enabled. D channel data is shifted in from the UID on this pin in 2 selectable modes: in TDM mode data is shifted in at the BCLK frequency (or half BCLK frequency in format 4) on the falling edges when the assigned time slot is active. In continuous mode data is shifted out at the DCLK frequency on the falling edge continuously. Clock input for the MICROWIRE control channel: data is shifted in and out on CI and CO pins with CCLK frequency following 2 modes. For each mode the CCLK polarity is indifferent. CCLK may be asynchronous with all the others UID clocks. MICROWIRE control channel serial input: Two bytes data is shifted out the UID on this pin on the rising or the falling edge of CCLK depending of the working mode. MICROWIRE control channel: serial output: two bytes data is shifted out the UID on this pin on the rising or the falling edge of CCLK depending of the working mode. When not enabled by CS low, CO is high impedance. Tx Super frame synchronization. The rising edge of SFSx indicates the beginning of the transmit superframe on the line. In NT mode SFSx is always an output. In LT mode SFSx is an input or an output depending of the SFS bit in CR2 register. When SFSx is input, it must be synchronous of FSa. Rx Super frame synchronization. The rising edge of SFSr indicates the begenning of the received superframe on the line. UID provides this output only when ESFR bit in CR4 register is to 1. Line Signal Detect output (default conf.): This pin is an open drain output which is normally in the high impedance state but pulls low when the device previously in the power down state receives a wake-up by Tone from the line. This signal is intended to be used to wake-up a micro-controller from a low power idle mode. The LSD output goes back in the high impedance state when the device is powered up. Interrupt output: Latched open-drain output signal which is normally high impedance and goes low to request a read cycle. Pending interrupt data is shifted out from CO at the following read-write cycle. Several pending interrupts may be queued internally and may provide several interrupt requests. INT is freed upon receiving of CS low and can goes low again when CS is freed. Chip Select input: When this pin is pulled low, data can be shifted in and out from the UID through CI & CO pins. When high, this pin inhibits the MICROWIRE interface. For normal read or write operation, CS has to be pulled low for 16 CCLK periods of time. 7/72
13
Bx
In
14
DCLK
Out
15
Dr
Out
16
Dx
In
17
CCLK
In
18
CI
In
19
CO
Out
22
SFSx
In Out
25
SFSr
Out
LSDb
Out
26
INTb
Out
27
CS
In
STLC5411
PIN FUNCTIONS (specific GCI mode)
Pin 6 7 Name FSa FSb S0 TEST2 11 Br In/Out In Out Out In In Out Description Input or Output depending of the configuration. FSa is a 8 KHz clock which indicates the start of the frame on Bx and Br. In NT/TE non auto-mode configuration, FSb is a 8 KHz pulse always indicating the second 64Kbit/sec channel of the frame on Br. When MO = 0 (LT/NT12 configuration): S0 associated with S1 and S2 selects a GCI channel number on Bx/Br. Input pin to select a transmission test in all auto mode configurations. TEST2 is associated with TEST1. 2B+D and GCI control channel open drain output. Data is shifted out (at the half BCLK frequency) on the first rising edge of BCLK during the assigned channels slot. Br is in high impedance state outside the assigned time slot and during the assigned time slot of a channel if it is disabled. Bit clock input or output depending of the configuration. When BCLK is an input, its frequency may be any multiple of 16 KHz from 512 KHz to 6176 KHz.. When BCLK is an output, its frequence is 512 KHz in NT1 auto and NTRR auto configurations, 1536 KHz in NT/TE configuration; In this case, BCLK is locked to the recovered clock received from the line. Input or Output BCLK is synchronous with FSa. Datas are shifted in and out (on Bx and Br) at the half the BCLK frequency. 2B+D and GCI control channel input. Data is sampled by the UID on the second falling edge of BCLK within the period of the bit, during the assigned channels time slot. General purpose programmable I/O configured by CR5 register in all non auto mode configurations. Input pin to select a transmission test in all auto mode configurations. TEST1 is associated with TEST2. General purpose programmable I/O configured by CR5 register in all non auto mode configurations. External control output pin in NT1 auto configuration. Normaly high, this pin is pulled low when an eoc message "operate 2B+D loopback" is recognized from the line. Local febe select: When tied to 1 the febe is locally looped back. See figure 10. General purpose programmable I/O configured by CR5 register in all non auto mode configurations. External control output pin in LTRR auto configuration. Normaly high, this pin is pulled low when an ARL command is received by the UID. External status input pin. In NT1 auto and NTRR auto configurations, this status is sent on the line through the ps2 bit. When MO = 0 (LT/NT12 configuration): S2 associated with S0 and S1 selects a GCI channel number on Bx/Br. When MO = 1: Configuration input pin. Is used associated with CONF1 to select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR auto. General purpose programmable I/O configured by CR5 register in all non auto mode configurations. External status input pin. In NT1 auto and NTRR auto configurations, this status is sent on the line through the ps1 bit. PLL1 can be disabled in LTRR onto configuration with this pin. When MO = 0 (LT/NT12 configuration): S1 associated with S0 and S2 selects a GCI channel number on Bx/Br. When MO = 1: Configuration input pin. Is used associated with CONF2 to select configuration NT/TE (non auto), NT1 auto, LTRR auto and NTRR auto.
12
BCLK
In Out
13
Bx
In
14
IO4 TEST1
In Out In In Out Out
15
IO3 EC
LFS 16 IO2 EC ES2 17 S2 CONF2
In In, Out Out In In In
18
IO1 ES1 PLLD
In Out In In In In
19
S1 CONF1
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STLC5411
PIN FUNCTIONS (specific GCI mode)
Pin 22 Name RFS In/Out In Description Remote febe select: When tied to 0 the remote febe is not transferred. When tied to 1 febe is transparently reported. See figure 10. Analog interface select for all auto mode configurations Rx Super frame synchronization. The rising edge of SFSr indicates the beginning of the received superframe on the line. UID provides this output only when ESFR bit in CR4 register is to 1 and LT/NT12 or NT/TE configuration is done. Line Signal Detect output (default conf.): This pin is an open drain output which is normally in the high impedance state but pulls low when the device previously in the power down state receives a wake-up by Tone from the line. This signal is intended to be used to wake-up a micro-controller from a low power idle mode. The LSD output goes back in the high impedance state when the device is powered up. Reset input pin with internal pull-up resistor. When pulled low, all registers of the UID are reset to their default values. UID is configured according to configuration inputs bias excluding MW input which must be maintained at the 0 volt. minimum recommended pulse length is 200s. Configuration input pin. When pulled low, GCI channel assigner is selected (channel number defined by inputs S0, S1, S2). When pulled high, UID is configured by pins CONF1 and CONF2.
25
AIS SFSr
In Out
LSDb
Out
26
RESb
In
27
M0
In
MULTIPLE FUNCTION PIN DESCRIPTION Pin 6: FSa
Function or In/Out conditions (*) MW(pin) = 1 CMS(cr1) = 1 CMS(cr1) = 0 CONF2(pin) = 1 MW(pin) = 0 MO(pin) = 1 CONF2(pin) = 0 MO(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 Function FSa FSa FSa FSa FSa FSa FSa In/Out Out In Out Out In Out In
(*) Only true if ANATST (internal test signal) = 0
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STLC5411
MULTIPLE FUNCTION PIN DESCRIPTION Pin 7: S0/FSb/TEST2
Function or In/Out conditions (*) MW(pin) = 1 CMS(cr1) = 1 CMS(cr1) = 0 CONF2(pin) = 1 MW(pin) = 0 MO(pin) = 1 CONF2(pin) = 0 MO(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 Function FSb FSb TEST2 FSb TEST2 TEST2 S0 In/Out Out In In Out In Out In
(*) Only true if ANATST (internal test signal) = 0
Pin 10: TSR~/SCLK/TCLK
Function or In/Out conditions (*) MW(pin) = 1 NTS(cr2) = 1 NTS(cr2) = 0 CONF2(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 NTS(cr2) = 1 NTS(cr2) = 0 CONF1(pin) = 1 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 Function SCLK TSR~ SCLK SCLK TSR~ SCLK SCLK TSR~ In/Out Out Out OD Out Out Out OD Out Out Out OD
(*) Only true if TDSPANA (internal test signal) = 0
Pin 12: BCLK
Function or In/Out conditions MW(pin) = 1 CMS(cr1) = 1 CMS(cr1) = 0 CONF2(pin) = 1 MW(pin) = 0 MO(pin) = 1 CONF2(pin) = 0 MO(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 Function BCLK BCLK BCLK BCLK BCLK BCLK BCLK In/Out Out In Out Out In Out In
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STLC5411
MULTIPLE FUNCTION PIN DESCRIPTION Pin 14: DCLK/IO4/TEST1/TSYNC [R+]
Function or In/Out conditions MW(pin) = 1 DEN(cr2) = 1 DEN(cr2) = 0 CONF1(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 IO4(cr5) = 1 IO4(cr5) = 0 CONF2(pin) = 1 CONF1(pin) = 0 IO4(cr5) = 1 IO4(cr5) = 0 DMO(cr2) = 1 DMO(cr2) = 0 Function DCLK TSYNC TSYNC TEST1 I4 O4 TEST1 I4 O4 In/Out Out Out Out In In Out In In Out
Pin 15: Dr/IO3/EC/LFS/TDOUT [R+]
Function or In/Out conditions (*) MW(pin) = 1 DEN(cr2) = 1 DEN(cr2) = 0 CONF1(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 IO3(cr5) = 1 IO3(cr5) = 0 CONF2(pin) = 1 CONF1(pin) = 0 IO3(cr5) = 1 IO3(cr5) = 0 Function Dr TDOUT EC I3 O3 LFS I3 O3 In/Out Out Out Out In Out In In Out
(*) Only true if TDSPANA (internal test signal) = 0
Pin 16: Dx/IO2/EC/ES2/TDIN [R+]
Function or In/Out conditions (*) MW(pin) = 1 DEN(cr2) = 1 DEN(cr2) = 0 CONF1(pin) = 1 CONF2(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 IO2(cr5) = 1 IO2(cr5) = 0 IO2(cr5) = 1 IO2(cr5) = 0 Function Dx TDIN ES2 I2 O2 EC ES2 I2 O2 In/Out In In In In Out Out In In Out
(*) Only true if TGSCEN (internal test signal) = 0
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MULTIPLE FUNCTION PIN DESCRIPTION Pin 17: CCLK/S2/CONF2
Function or In/Out conditions MW(pin) = 1 MW(pin) = 0 MO(pin) = 1 MO(pin) = 0 Function CCLK CONF2 S2 In/Out In In In
Pin 18: CI/IO1/ES1/PLLD [R+]
Function or In/Out conditions MW(pin) = 1 CONF1(pin) = 1 CONF2(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 CONF1(pin) = 0 CONF1(pin) = 1 CONF1(pin) = 0 IO1(cr5) = 1 IO1(cr5) = 0 IO1(cr5) = 1 IO1(cr5) = 0 Function CI ES I1 O1 PLLD ES1 I1 O1 In/Out In In In Out In In In Out
Pin 19: CO/S1/CONF1
Function or In/Out conditions MW(pin) = 1 MW(pin) = 0 MO(pin) = 1 MO(pin) = 0 Function CO CONF1 S2 In/Out Out In In
Pin 22: SFSx/RFS [R+]
Function or In/Out conditions NTS(cr2) = 1 MW(pin) = 1 NTS(cr2) = 0 MO(pin) = 1 MW(pin) = 0 MO(pin) = 0 CONF2(pin) = 1 CONF2(pin) = 0 NTS(cr2) = 1 NTS(cr2) = 0 SFS(cr2) = 1 SFS(cr2) = 0 SFS(cr2) = 1 SFS(cr2) = 0 Function SFSx SFSx SFSx SFSx RFS SFSx SFSx SFSx In/Out Out Out In Out In Out Out In
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STLC5411
MULTIPLE FUNCTION PIN DESCRIPTION Pin 25: LSD/SFSr/AIS
Function or In/Out conditions MW(pin) = 1 CONF1(pin) = 1 MO(pin) = 1 MW(pin) = 0 CONF2(pin) = 0 MO(pin) = 0 ESFR(cr4) = 1 ESFR(cr4) = 0 CONF2(pin) = 1 CONF1(pin) = 0 ESFR(cr4) = 1 ESFR(cr4) = 0 ESFR(cr4) = 1 ESFR(cr4) = 0 Function SFSr LSD AIS SFSr LSD AIS SFSr LSD In/Out Out OD Out OD In Out OD Out OD In Out OD Out OD
Pin 26: INT/RES [R+]
Function or In/Out conditions MW(pin) = 1 MW(pin) = 0 Function INT MO In/Out Out OD In
Pin 27: CS/MO
Function or In/Out conditions MW(pin) = 1 MW(pin) = 0 Function CS MO In/Out In In
PIN28: MW Notes: [R+] = Pull up Resistor : Out OD = Open Drain Output
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FUNCTIONAL DESCRIPTION Digital Interfaces STLC5411 provides a choice between two types of digital interface for both control data and (2 B+D) basic access data. These are: a) General Circuit Interface: GCI. b) Microwire/Digital System Interface: W/DSI The device will automatically switch to one of them by sensing the MW input pin at the Power up. W/DSI MODE Microwire control interface The MICROWIRE interface is enabled when pin MW equal one. Internal registers can be written or read through that control interface. It is constituted of 5 pins: CI: CO: CCLK: CS: INT: data in data output data clock input Chip Select input Interrupt output while CS is low) . When CS is high, the CO pin is in the high impedance state. Write cycle The format to write a 8 bits message into the UID is:
A7 A6 A5 A4 A3 A2 A1 A0
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
2nd byte A7-A1: A0: D7-D0: Register Address Write/Read back Indicator Register Content
Transmission of data onto CI & CO is enabled when CS input is low. A Write cycle or a Read cycle is always constituted of two bytes. CCLK must be pulsed 16 times while CS is low. Transmission of data onto CI & CO is enabled following 2 modes. - MODE A: the first CCLK edge after CS falling edge (and fifteen others odd CCLK edges) are used to shift in the CI data, the even edges being used to shift out the CO data. - MODE B: the CCLK first edge after CS falling edge (and the fifteen others odd CCLK loss) are used to shift out the CO data, the even edges being used to shift in the CI data. For each modes the first CCLK edge after CS falling edge can be positive or negative: the UID automaticaly detects the CCLK polarity. Mode A is the default value. To select the mode B, write MWPS register. You can write in the UID on CI while the UID send back a register content to the microprocessor. If the UID has no message to send, it forces the CO output to all zero's. If the UID is to be read (status change has occured in the UID or a read-back cycle has been requested by the controller), it pulls the INT output low until CS is provided. INT high to low transition is not allowed when CS is low (the UID waits for CS high if a pending interrupt occurs
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After the first byte is shifted in, Register address is decoded. A0 set low indicates a write cycle: the content of the following received byte has to be loaded into the adressed register. A0 set high indicates a read-back cycle request and the byte following is not significant. The UID will respond to the request with an interrupt cycle. It is then possible for the microprocessor to receive the required register content after several other pending interrupts. To write a 12bits message, the difference is: limited address field: A7 - A4 extended data field (D11 - D8): A3 - A0. The Write/Read back indicator doesn't apply; to read and write a 12 bits register two addresses are necessary. Read cycle When UID has a register content to send to the microprocessor, it pulls low the INT output to request CS and CCLK signals. Note that the data to send can be the content of a Register previously requested by the microprocessor by means of a read-back request. The format of the 8 bits message sent by the UID is:
A7 A6 A5 A4 A3 A2 A1 A0
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
2nd byte Register Address forced to 1 if read back forced to 0 if spontaneous D7-D0: Register Content A7-A1: A0:
STLC5411
To read a 12 bits message, the difference is: limited address field: A7 - A4 extended data field (D11 - D8): A3 - A0. The Write/Read back indicator doesn`t exit. DIGITAL SYSTEM INTERFACE Two B channels, each at 64 kbit/s and one D channel at 16 kbit/s form the Basic access data. Basic access data is transferred on the Digital System Interface with several different formats selectable by means of the configuration register CR1. The DSI is basically constituted of 5 wires (see fig.2 and 3): BCLK Bx Br FSa FSb bit clock data input to transmit to the line data output received from the line Transmit Frame sync Receive Frame sync Dx and Dr pins (D port disabled or enabled in TDM mode respectively). Format 4: is a GCI like format excluding Monitor channel and C/I channel. The 2B+D data transfer is assigned to the first 26 bits of the frame on Br and Bx I/O pins. Channels are assigned as follows. B1(8 bits) B2(8 bits), 8 bits ignored, D(2 bits), with remaining bits ignored up to the next frame sync pulse. When the Digital Interface clocks are selected as inputs, FSa must be a 8 kHz clock input which indicates the start of the frame on the data input pin Bx. When the Digital Interface clocks are selected as outputs, FSa is an 8 kHz output pulse conforming to the selected format which indicates the frame beginning for both Tx and Rx directions. When the Digital Interface clocks are selected as inputs, FSb is a 8 kHz clock input which defines the start of the frame on the data ouput pin Br. When the Digital Interface clocks are selected as outputs, FSb is a 8 kHz output pulse indicating the second 64kbit/s slot. Two phase-relations between the rising edge of FSa/FSb and the first (or second for FSb as output) slot of the frame can be selected depending on format selected: Delayed timing mode or non Delayed timing mode. Non delayed data mode is similar to long frame timing on the COMBOI/II series of devices: The first bit of the frame begins nominally coincident with the rising edge of FSa/b. When output, FSa is coincident with the first 8 bits wide time-slot while FSb is coincident with the second 8 bits wide time-slot. Non delayed mode is not available in format 2. Delayed timing mode, which is similar to short frame sync timing on COMBO I/II, in which the FSa/b input must be set high at least a half cycle of BCLK earlier the frame beginning. When output, FSa 1bit wide pulse indicates the first 8 bits wide time-slot while FSb indicates the second. Delayed mode is not available in format 4. 2B+D basic access data to transmit to the line can be shifted in at the BCLK frequency on the falling edges during the assigned time-slots. When D channel port is enabled, only B1 & B2 data is shifted in during the assigned time slots. In format 4, data is shifted in at half the BCLK frequency on the receive falling edges. 2B+ D basic access data received from the line can be shifted out from the Br output at the BCLK frequency on the rising edges during the assigned time-slots. Elsewhere, Br is in the high impedance state. When the D channel port is enabled, only B1 & B2 data is shifted out from Br. In Format 4, data is shifted out at half the BCLK frequency on the transmit rising edges; there is 1.5 period delay between the rising transmit edge and the receive falling edge of BCLK.
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It is possible to separate the D channel from the B channels and to transfer it on a separate Digital Interface constituted of 2 pins: Dx Dr D channel data input D channel data ouput
The TDM (Time Division Multiplex) mode uses the same bit and frame clocks as for the B channels. The continuous mode uses an internally generated 16 kHz bit clock output: DCLK D channel clock output For all formats when D channel port is enabled "continuous mode" is possible. When the D channel port is enabled in TDM mode, D bits are assigned according to the related format on Dx and Dr . STLC5411 provides a choice of four multiplexed formats for the B and D channels data as shown in fig.2 and 3. Format 1: the 2B+D data transfer is assigned to the first 18 bits of the frame on Br and Bx I/0 pins. Channels are assigned as follows: B1(8 bits), B2(8 bits), D(2 bits), with the remaining bits ignored until the next Frame sync pulse. Format 2: the 2B+D data transfer is assigned to the first 19 bits of the frame on Br and Bx I/O pins. Channels are assigned as follows: B1(8 bits), D(1 bit), 1 bit ignored, B2(8 bits), D(1 bit), with the remaining bits ignored until the next frame sync pulse. Format 3: B1 and B2 Channels can be independently assigned to any 8 bits wide time slot among 64 (or less) on the Bx and Br pins. The transmit and receive directions are also independent. When TDM mode is selected, the D channel can be assigned to any 2 bits wide time slot among 256 on the Bx and Br pins or on the
STLC5411
Bit Clock BCLK determines the data shift rate on the Digital Interface. Depending on mode selected, BCLK is an input which may be any multiple of 8 kHz from 256 kHz to 6176 kHz or an output at a frequency depending on the format and the frequency selected. Possible frequencies are: 256 KHz, 512 KHz, 1536 KHz, Figure 2: DSI Interface formats: MASTER mode. 2048 KHz, 2560 KHz. In format 4 the use of 256kHz is forbidden. BCLK is synchronous with FSa/b frame sync signal. When output, BCLK is phased locked to the recovered clock received from the line.
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Figure 3: DSI Interface formats: SLAVE mode.
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STLC5411
GCI MODE The GCI is a standard interface for the interconnection of dedicated ISDN components in the different equipments of the subscriber loop : In a Terminal, GCI interlinks the STLC5411, the ISDN layer 2 (LAPD) controller and the voice/data processing components as an audio-processor or a Terminal Adaptor module. In NT1-2, PABX subscriber line card, or central office line card (LT), GCI interlinks the UID, the ISDN Layer 2 (LAPD) controllers and eventually the backplane where the channels are multiplexed. In NT1, GCI interlinks SID-GCI and STLC5411, via automode (NT1-auto). In Regenerators, GCI links both STLC5411 UID in automode (NT-RRauto, LT-RR-auto). (See Fig. 4a) Frame Structure 2B+D data and control interface is transferred in a time-division multiplexed mode based on 8 kHz frame structure and assigned to four octets per frame and direction.(see fig.4b). The 64 kbit/s channels B1 and B2 are conveyed in the first two octets; the third octet (M: Monitor) is used for transferring most of the control and status registers; the fourth octet (SC: Signalling & Control) contains the two D channel bits, the four C/I (command/lndicate) bits controlling the activation/deactivation procedures, and the E & A bits which support the handling of the Monitor channel. Figure 4a: GCI configurations of the UID. These four octets per frame serving one ISDN subscribers line form a GCI Channel. One GCI channel calls for a bit rate of 256 kbit/s. In NT1-2s or subscriber Line Cards up to 8 GCI channels may be carried in a frame of a GCI multiplex. The bit rate of a GCI multiplex may be from 256 kbit/s and up to 3088 kbit/s. Adjacent 4-octet slots from the frame start are numbered 0 to 7. The GCI channel takes the number of the slot it occupies. Spare bits in the frame beyond 256 bits from the frame start will be ignored by GCI compatible devices but may be used for other purposes if required (see Fig.4c). GCI channel number is selected by biasing pins S0,S1,S2. Physical Links Four physical links are used in the GCI. Transmitted data to the line: Bx Received data from the line: Br Data clock: BCLK Frame Synchronization clock: FSa GCI is always synchronized by frame and data clocks derived by any master clock source. A device used in NT mode can deliver clock sources able to synchronize GCI, either directly, or via a local Clock Generator synchronized on the line by means of the SCLK 15.36 MHz output clock. Frame clock and data clock could be independent of the internal devices clocks. Logical one on the Br output is the high impedance state while logical zero is low voltage. For E and A bits, active state is voltage Low while inactive state is high impedance state.
Figure 4a: GCI configurations of the UID
SID-GCI
SID-GCI
NT1-AUTO
LT-RR-AUTO
NT-RR-AUTO
LT
TERMINAL
S
NT1 NT
U
REPET OR
U
LINE TERMINATI ON
PRIVATE TERMINAL OR NT1-2
U
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STLC5411
Figure 4b: GCI interface format.
Figure 4b:
GCI interface format
GCI CHANNEL 0 GCI CHANNEL 1 GCI CHANNEL 7
B1
B2 8
M 8
D C/I A E 2 4 2
B1 8
B2 8
M 8
D C/I A E 2 4 2
B1 8
B2 8
M 8
D C/I A E 2 4 2
Bx/Br
8
FSa
8 KHz
BCLK
SLAVE MODE
GCI CHANNEL 0
B1
B2 8
M 8
D C/I A E 2 4 2 FREE
Bx/Br
8
FSa
8 KHz
FSb
BCLK
MASTER MODE (BCLK = 1.536MHz)
MASTE R MODE
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STLC5411
Figure 4c: GCI multiplex examples, (slave mode).
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STLC5411
Data is transmitted in both directions at half the data clock rate. The information is clocked by the transmitter on the front edge of the data clock and can be accepted by the receiver after 1 to 1.5 period of the data clock. The data clock (BCLK) is a square wave signal at twice the data transmission frequency on Bx and Br with a 1 to 1 duty cycle. The frequency can be choosen from 512 to 6176 kHz with 16 kHz modularity. Data transmission rate depends only on the data clock rate. Table 1: GCI Configuration selection.
Pin Number Pin name LT/NT12* 28 27 19 17 7 18 16 15 14 22 MW M0 S1/CONF1 S2/CONF2 S0/FSb/TEST2 IO1/ES1 IO2/ES2 IO3/EC IO4/TEST1 SFSx/RFS 0 0 S1 S2 S0 IO1 IO2 IO3 IO4 SFSx NT/TE 0 1 0 1 FSb IO1 IO2 IO3 IO4 SFSx Configuration NT1-AUTO 0 1 1 1 TEST2 ES1 ES2 EC TEST1 SFSx LT-RR-AUTO 0 1 1 0 TEST2 PLDD EC LFS TEST1 RFS NT-RR-AUTO 0 1 0 0 TEST2 ES1 ES2 LFS TEST1 RFS
The Frame Clock FSa is a 8 kHz signal for synchronization of data transmission. The front edge of this signal gives the time reference of the first bit in the first GCI input and output channel, and reset the slot counter at the start of each frame When some GCI channels are not selected on devices connected to the same GCI link, these time slots are free for alternative uses. GCI configuration selection is done by biasing of input pins MW, M0, CONF1, CONF2 according to TABLE1.
* Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode. When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is automatically selected When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected. * * Connected to VCC through internal pull-up resistors.
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STLC5411
Monitor channel The Monitor channel is used to write and read all STLC5411 internal registers. Protocol on the Monitor channel allows a bidirectional transfer of bytes between UID and a control unit with acknowledgement at each received byte. Bytes are transmitted on the Br output and received on the Bx input in the Monitor channel time slot. A write or read cycle is always constituted of two bytes.(see fig. 5). It is possible to operate several write or read cycles within a single monitor message. Note: Special format is used for EOC channel. Write cycle The format to write a message into the UID is:
A7 A6 A5 A4 A3 A2 A1 A0
A7-A1: A0: D7-D0:
Register Address forced to 0 is spontaneous interrupt, forced to 1 if readback Register Content
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
2nd byte A7-A1: A0: D7-D0: Register Address Write/Read back Indicator Register Content
After the first byte is shifted in, Register address is decoded. A0 set low indicates a write cycle: the content of the following received byte has to be loaded into the addressed register. A0 set high indicates a read-back cycle request. the second byte content is not significative. STLC5411 will respond to the request by sending back a message with the register content associated with its own address. It is then possible for the microprocessor to receive the required register content after several other pending messages. To avoid any loss of data, it is recommended to operate only one read-back request at a time. Note: Special format is used for EOC channel. Read cycle When UID has a register content to send to the controller, it send it on the monitor channel directly. Note that the data to send can be the content of a Register previously requested by the controller by means of a read-back request. The format of the message sent by the UID is:
A7 A6 A5 A4 A3 A2 A1 A0
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
2nd byte
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Exchange Protocol STLC5411 validates a received byte if it is detected two consecutive times identical. (see fig. 5) The exchange protocol is identical for both directions. The sender uses the E bit to indicate that it is sending a Monitor byte while the receiver uses A bit to acknowledge the received byte.When no message is transferred, E bit and A bit are forced to inactive state. A transmission is started by the sender (Transmit section of the Monitor channel protocol handler) by putting the E bit from inactive to active state and by sending the first byte on Monitor channel in the same frame. Transmission of a message is allowed only if A bit sent from the receiver has been set inactive for at least two consecutive frames. When the receiver is ready, it validates the incoming byte when received identical in two consecutive frames. Then, the receiver set A bit from the inactive to the active state (preacknowledgement) and maintain active at least in the following frame (acknowledgement). If validation is not possible (two last bytes received are not identical) the receiver aborts the message by setting the A bit active for only a single frame.The second byte can be transmitted by the sender putting the E bit from the active to the inactive state and sending the second byte on the Monitor channel in the same frame . The E bit is set inactive for only one frame. If it remains inactive more than one frame, it is an end of message. The second byte may be transmitted only after receiving of the pre-acknowledgement of the previous byte . Each byte has to be transmitted at least in two consecutive frames. The receiver validates the current received byte as for the first one and then set the A bit in the next two frames first from the active state to the inactive state (pre-acknowledgement) and back to the active (acknowledgement). If the receiver cannot validates the received current byte (two bytes received not identical)it pre-acknowledges normally but let the A bit in the inactive state in the next frame which indicates an abort request . If a message sent by the UID is aborted, the UID will send again the complete message until receiving of an acknowledgement . A message received by the UID can be acknowledged or aborted with flow Control. The most significant bit (MSB) of Monitor byte is sent first on the Monitor channel. E & A bits are active low and inactive state on Br is 5 V. When no byte is transmitted, Monitor channel time slot
STLC5411
on Br is in the high impedance state. A 24 ms timer is implemented in the UID. This timer (when enabled) starts each time the sender starts a byte sending and waits for a pre acknowledgement. C/I channel The C/I channel is used for TXACT and RXACT registers write and read operation. However, it is possible to access to ACT registers by monitor Figure 5: GCI Monitor channel messaging examples. channel: this access is controled by the CID bit in CR2 register. The four bits code (C1,C2,C3,C4) of TXACT register can be loaded in the UID by writing permanently this code in the C/I channel time-slot on Bx input every GCI frames. The UID takes into account the received code when it has been received two consecutive times identical. When a status change occurs in the RXACT register, the new (C1,C2,C3,C4) code is sent in the C/I channel time-slot on Br output every GCI frames. This
M E A
X
M1
M1
M2
M2
X
X
X
1st byt e (M1) Ready for a message pre-a ck (M1) ack (M1)
2n d byte (M2) pr e-ac k (M2) ack (M2)
3rd byt e?? (X)
EOM pre- ack?? (X) Rea dy for a new messag e
TWO BYTES MESSAGE - NORMAL TRANSMISSION
X
M1
M1
M2
M2
X
X
X
M E A
X
M1
M1
M2
1st byt e (M1) Rea dy fo r a message pre -ack (M1)
2nd byte (M2) ack (M1) pre -ack (M2)
3r d byte? ? (X) ab ort (M2)
EOM (or ab ort ack)
1st byte (M1) pre -ack (M1)
Read y for retr ansmission
TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED
E & A BITS TIMING
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STLC5411
code is sent permanently by the UID until a new status change occurs in RXACT register. C1 bit is sent first to the line. LINE CODING AND FRAME FORMAT 2B1Q coding rule requires that binary data bits are grouped in pairs so called quats (see Tab.2). Each quat is transmitted as a symbol, the magnitude of which may be 1 out 4 equally spaced voltage levels (see Fig. 6). +3 quat refers to the nominal pulse waveform specified in the ANSI standard. Other quats are deduced directly with respect of the ratio and keeping of the waveform. The frame format used in UID follows ANSI specification (see Tab. 3 and 4). Each complete frame consists of 120 quats, with a line baud rate of 80 kbaud, giving a frame duration of 1.5ms. A nine quats lenght sync-word defines the framing boundary. Furthermore, a Multiframe consisting of 8 frames is defined in order to provide sub-channels within the spare bits M1 to M6. Inversion of the syncword defines the multiframe boundary. In LT, the transmit multiframe starting time may be synchronized by means of a 12 ms period of time pulse on the SFSx pin selected as an input (bit SFS in CR2); If SFSx is selected as an output, SFSx provides a square wave signal with the rising edge indicating the multiframe starting time. In NT, the transmit multiframe starting time is provided on SFSx output by the rising edge of a 12 ms period of time square wave signal. LT or NT, when pin 25 is selected as SFSr by mean of bit ESFr in CR4, SFSr is a square wave open drain output indicating the received superframe on the line. (see figure 7). Prior to transmisssion, all data, with the exception of the sync-word,is scrambled using a self-synchronizing scrambler to perform the specified 23rd-order polynomial. Descrambling is included in the receiver. Polynomial is different depending on the direction LT to NT or vice versa. tion, results in a signal amplitude of 2.5V pk nomince on the line for single quats of the +3 level. (see output pulse template fig.8). Short-circuit protection is included in the output stage; over-voltage protection must be provided externally. In LT applications, the Network reference clock given by the FSa 8kHz clock input synchronizes the transmitted data to the line. The Digital Interface normally accepts BCLK and FSa signals from the network, requiring the selection of Slave Mode in CR1. A Digital Phase-Locked Loop (DPLL#1) on the UID allows the SCLK frequency to be plesiochronous with respect to the network reference clock (8 kHz FSa input). With a tolerance on the XTAL1 oscillator of 15.36 MHz +/100 ppm, the lock-in range of DPLL1 allows the network clock frequency to deviate up to +/50ppm from nominal. In LT, if DSI is selected in Master mode, (Microwire only, bit CMS = 1 in CR1), BCLK and FSa signals are outputs frequency synchronized to XTAL1 input, DPLL#1 is disabled. In NT applications, data is transmitted to the line with a phase deviation of half a frame relative to the received data as specified in the ANSI standard. RECEIVE SECTION The receive input signal should be derived from the transformer by a coupling circuit as shown in the Application section. At the front end of the receive section is a continuous filter which limits the noise bandwidth to approximately 100kHz. Then, an analog pre-canceller provides a degree of echo cancellation in order to limit the dynamic range of the composite signal which noise bandwidth limited by a 4th order Butterworth switched capacitor low pass filter. After an automatic gain control, a 13bits A/D converter then samples the composite received signal before the echo cancellation from local transmitter by means of an adaptive digital transversal filter. The attenuation and distortion of the received signal from the farend, caused by the line, is equalized by a second adaptive digital filter configured as a Decision Feedback Equalizer (DFE), that restores a flat channel response with maximum received eye opening over a wide spread of cable attenuation characteristics. A timing recovery circuit based on a DPLL (Digital Phase-Locked Loop) recovers a very low-jitter clock for optimum sampling of the received symbols. The 15.36MHz crystal oscillator (or the logic level clock input) provides the reference clock for the DPLL. In NT configuration, SCLK output provides a very low jitterized 15.36MHz clock synchronized from the line. Received data is then detected and flywheel synchronization circuit searches for and locks onto
TRANSMIT SECTION Data transmitted to the line consists of the 2B+D channel data received from the Digital Interface through an elastic data buffer allowing any phase deviation with the line, the activation/deactivation bits (M4) from the on-chip activation sequencer, the CRC code plus maintenance data (eoc channels) and other spare bits in the overhead channels (M4, M5, M6). Data is multiplexed and scrambled prior to addition of the sync-word, which is generated within the device. A pulse waveform synthesizer then drives the transmit filter, which in turn passes the line signal to the line driver. The differential line-driver Outputs, LO+, LO- are designed to drive a transformer through an external termination circuit. A 1:1.5 transformer designed as shown in the Application sec24/72
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the frame and superframe syncwords. STLC5411 is frame-synchronized when two consecutive synchwords have been consecutively detected. Frame lock will be maintained until six consecutive errored sync-words are detected, which will cause the flywheel to attempt to re-synchronize. If a loss of frame sync condition persists for 480ms the device will cease searching, cease transmitting and go automatically into the RESET state, ready for a further cold start. When UID is framesynchronized, it is superframe-locked upon the first superframe sync-word detection. No loss of superframe sync-word is provided. While the receiver is synchronized, data is descrambled using the specified polynomial, and individual channels demultiplexed and passed to their respective processing circuits: user's 2B+D channel data is transmitted to the Digital Interface through an elastic data buffer allowing any phase deviation with the line; the activation/deactivation bits (M4) are transmitted to the on-chip activation sequencer; CRC is transmitted to CRC checking section while maintenance data (eoc) and other spare bits in the overhead channels (M4, M5, M6) are stored in their respective Rx registers. In NT applications, if the Digital Interface is selected in master mode (see CR1) BCLK and FSa clock outputs are phase-locked to the recovered clock. If it is selected in Slave mode ie for NT1-2 application, the on-chip elastic buffers allow BCLK and FSa to be input from an external source, which must be frequency locked to the received line signal ie using the SCLK output but with arbitrary phase. any of the Overhead bit Transmit Registers is resynchronized internally to the next available complete superframe or half superframe, as appropriate. Embedded Operation Channel (EOC) The EOC channel consists of two complete 12 bits messages per superframe, distributed through the M1, M2 and M3 bits of each frame. Each message is composed of 3 fields; a 3 bit address identifying the message destination/origin, a 1 bit indicator for the data mode i.e. encoded message or raw data, and an 8 bits information field. The Control Interface (Microwire or Monitor channel in GCI) provides access to the complete 12 bits of every message in TX and RX EOC registers. When non-auto mode is selected, UID does not interpret the received eoc messages e.g. "send corrupted CRC"; therefore the appropriate command instruction must be written to the device e.g. "set to one bit CTC in register CR4". It is possible to select a transparent transmission mode in which the EOC channel can be considered as a transparent 2 kbit/s channel. See OPR register description for details. When auto-mode is selected in GCI configuration, UID performs automatic recognition / acknowledgement of the EOC messages sent by the network according to processing defined in ANSI standard and illustrated in figure 9. When UID recognizes a message with the appropriate address and a known command, it performs automatically the relevant action inside the device and send a message at the digital interface as appropriate. Table 5 gives the list of recognized eoc messages and associated actions. When NT-RR-AUTO configuration is selected, eoc addressing is processed according to appendix E of T1E1.601 standard: - If address of the eoc message received from LT is in the range of 2 to 6, UID decrements address and pass the message onto GCI. - If address of the eoc message received from GCI is in the range of 1 to 5, UID increments address and pass the message onto the line toward LT. - If data/msg indicator is set to 0, UID pass data on transparently with eoc address as described above. M4 channel M4 bit positions of every frame is a channel in which are transmitted data bits loaded from the TXM4 transmit register and from the on-chip activation sequencer once the superframe. On the receive side, M4 bits from one complete superframe are first validated and then stored in the RXM4 Receive Register or transmitted to on-chip activation sequencer. See OPR, TXM4 and RXM4 reg25/72
ELASTIC BUFFERS The UID buffers the 2B+D data in elastic fifos which are 3 line-frames deep in each direction. When the Digital Interface is a timing slave, these FIFOs compensate for relative jitter and wander between the Digital Interface and the line. Each buffer can absorb wander up to 18s at 80 KHz max without "slip". This is particulary convenient for NT1-2 or PABX application in case the local reference clock is jitterized and wandered relative to the incoming signal from the line.
MAINTENANCE FUNCTIONS M channel In each frame there are 6 "overhead" bits assigned to various control and maintenance functions. Some programmable processing of these bits is provided on chip while interaction with an external controller provides the flexibility to take full advantage of the maintenance channels. See OPR, TXM4, TXM56, TXEOC, RXM4, RXM56, RXEOC registers description fo details. New data written to
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isters description for details. When NT1-AUTO or NT-RR-AUTO mode is selected, bits ps1 and ps2 in M4 channel are controlled directly by biasing input pins ES1 and ES2 respectively. e.g. ps1 is sent continuously to the line equal 0 when ES1 input is forced at 0 Volt. Spare M5 and M6 bits The spare bit positions in the M5 and M6 field form a channel in which are transmitted data bits loaded from the TXM56 transmit register. On the receive side, the spare bits in the M5 and M6 field are first validated and then stored in the RXM56 receive register. See OPR, TXM56 and RXM56 registers description for details. CRC calculation/checking In transmit direction, an on-chip CRC calculation circuit automatically generates a checksum of the 2B+D+M4 bits using the specified 12th order polynomial. Once per superframe, the CRC is transmitted in the M5 and M6 bit positions. In receive direction, a checksum is again calculated on the same bits as they are received and, at the end of the superframe compared with the received CRC. The result of this comparison generates a "Far End Block Error" bit (febe) which is transmitted back towards the other end of the Line in the next but one superframe and an indication of Near End Block Error is sent to the system by means of Register RXM56. If there is no error in superframe, febe is set = 1, and if there is one or more errors, febe is set = 0. UID also includes two 8 bits Block Error Counters associated with the febe bits transmitted and received. It is then possible to select one Error Counter per direction or to select only one counter for both by means of bit C2E in OPR register. Block error counting is always enabled but it is possible to disabled the threshold interrupt and/or to enable/disable the interrupt issued at each received or transmitted block error detection. See OPR register for details. Loopbacks Six transparent or non transparent channel loopbacks are provided by UID. It is therefore possible to operate any loopback on B1, B2 and D channels line to line or DSI/GCI to DSI/GCI. Command are grouped in CR3 register. In addition to the channel loopbacks in LT modes, a complete transparent loopback operated at the transmission side of UID allows the device to activate through an appropriate sequence with the complete data stream looped-back to the receiver. Therefore, most of analog/digital clock and data recovery circuits are tested. After activation completed, an AI status indication is reported. Complete loopback is enabled with ARL command in TXACT register.
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Table 2: 2B1Q Encoding of 2B+ D Fields.
Data Bit Pair Quat # (relative) # Bits # Quats Time BI b 11b12 q1 b13 b 14 q2 8 4 b 15 b16 q3 b17 b 18 q4 b 21b22 q5 b23 b 24 q6 8 4 Bg b25 b26 q7 b27 b28 q8 D d1d 2 q9 2 1
Where: b11 = first bit of B1 octet as received at the S/T interface b18 = last bit of BI octet as received at the S/T interface b21 = first bit of B2 octet as received at the S/T interface b28 = last bit of B2 octet as received at the S/T interface d1 d2 = consecutive D-channel bits (d1 is first bit of pair as received at the S/T interface) qi = ith quat relative to start of given 18-bit 2B+D data field. NOTE: There are 12 2B+D 18-bit fields per 1.5 msec basic frame.
Table 3: Network-to-NT 2B1Q Superframe Technique and Overhead Bit Assignments.
FRAMING Quat Positions Bit Positions Super Frame # A Basic Frame # 1 2 3 4 5 6 7 8 B,C,... Sync Word ISW SW SW SW SW SW SW SW 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D M1 eoca1 eocdm eoci3 eoci6 eoca1 eocdm eoci3 eoci6 M2 eoca2 eoci1 eoci4 eoci7 eoca2 eoci1 eoci4 eoci7 M3 eoca3 eoci2 eoci5 eoci8 eoca3 eoci2 eoci5 eoci8 M4 act dea 1 1 1 1 uoa aib M5 1 1 crc1 crc3 crc5 crc7 crc9 crc11 M6 1 febe crc2 crc4 crc6 crc8 crc10 crc12 1-9 1-18 2B+D 10-117 19-234 118s 235 118m 236 Overhead Bits (M1-M6) 119s 237 119m 238 120s 239 120m 240
NT-to-Network superframe delay offset from Network-to-NT superframe by 60 2 quats (about 0.75 ms). All bits than the Sync Word are scrambled. Symbols & Abbreviations:
"1" eoc reserve = reserved bit for future standard; set = 1 embedded operations channel a = address bit dm = data/message indicator i = information (data/message) synchronization word act crc activation bit cyclic redundancy check: covers 2B+D & M4 1 = most significant bit 2 = next most significant bit etc
SW
febe far end block error bit (set = 0 for errored superframe) dea uoa aib deactivation bit (set = 0 to announce deactivation) u only activation bit (set = 1 to activate S/T) alarm indication bit (set = 0 to indicate interruption) 27/72
ISW inverted synchronization word s m sign bit (first) in quat magnitude bit (second) in quat
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Table 4: NT-to-Network 2B1Q Superframe Technique and Overhead Bit Assignments.
FRAMING Quat Positions Bit Positions Super Frame # 1 Basic Frame # 1 2 3 4 5 6 7 8 2,3,... Sync Word ISW SW SW SW SW SW SW SW 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D 2B+D M1 eoca1 eocdm eoci3 eoci6 eoca1 eocdm eoci3 eoci6 M2 eoca2 eoci1 eoci4 eoci7 eoca2 eoci1 eoci4 eoci7 M3 eoca3 eoci2 eoci5 eoci8 eoca3 eoci2 eoci5 eoci8 M4 act ps 1 ps 2 ntm cso 1 sai 1 M5 1 1 crc1 crc3 crc5 crc7 crc9 crc11 M6 1 febe crc2 crc4 crc6 crc8 crc10 crc12 1-9 1-18 2B+D 10-117 19-234 118s 235 118m 236 Overhead Bits (M1-M 6) 119s 237 119m 238 120s 239 120m 240
NT-to-Network superframe delay offset from Network-to-NT superframe by 60 2 quats (about 0.75 ms). All bits than the Sync Word are scrambled. Symbols & Abbreviations:
"1" eoc reserve = reserved bit for future standard; set = 1 embedded operations channel a = address bit dm = data/message indicator i = information (data/message) synchronization word ps1, ps2 ntm power status bits (set = 0 to indicate power problems) NT in Test Mode bit (set = 0 to indicate test mode
SW
cso crc
cold-start-only bit (set = 1 to indicate cold-start-only cyclic redundancy check: covers 2B+D & M4 1 = most significant bit 2 = next most significant bit etc
ISW inverted synchronization word
s m act
sign bit (first) in quat magnitude bit (second) in quat activation bit
febe far end block error bit (set = 0 for errored superframe) sai S/T interface activation indication bit.
Figure 6: Example of 2B1Q Quaternary Symbols.
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Figure 7: Superframe I/O pin SFS
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Figure 8: Normalized output pulse form
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Figure 9: EOC message processing mode.
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Figure 10: CRC Errors Processing (auto-mode)
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Table 5: EOC message processing: local actions.
NT1-AUTO: (eoc address 000 or 111) Message Operate 2B+D loopback Operate B1channel Loopback Operate B2 channel Loopback Request Corrupted CRC Notify of Corrupted CRC Return to Normal Hold state Unable to comply Code 0101 0000 0101 0001 0101 0010 0101 0011 0101 0100 1111 1111 0000 0000 1010 1010 Local action Send ARL code on C/I channel to operate Loopback 2 in SID-GCI. Forces EC output low Performs transparent loopback on B1 channel identical to LB1 command in CR3 Performs transparent loopback on B2 channel identical to LB2 command in CR3 Performs corruption of the transmit CRC identical to CTC command in CR4. No action taken. Send back to the Network unable to comply message. All outstanding EOC operations are reset. All outstanding EOC operations maintained in their present state Sent by UID to indicate that the message is not in its menu
NT-RR-AUTO: (eoc address 001 or 111) Message Operate 2B+D loopback Operate B1channel Loopback Operate B2 channel Loopback Request Corrupted CRC Notify of Corrupted CRC Return to Normal Hold state Unable to comply Code 0101 0000 0101 0001 0101 0010 0101 0011 0101 0100 1111 1111 0000 0000 1010 1010 Local action Send ARL code on C/I channel to operate Loopback 1A in UID configured in LT-RR-AUTO. Forces EC output low. Performs transparent loopback on B1 channel identical to LB1 command in CR3 Performs transparent loopback on B2 channel identical to LB2 command in CR3 Performs corruption of the transmit CRC identical to CTC command in CR4. No action taken. Send back to the Network unable to comply message. All outstanding EOC operations are reset. All outstanding EOC operations maintained in their present state Sent by UID to indicate that the message is not in its menu
IDENTIFICATION CODE (GCI) The identification register is implemented at the two addresses 80 H and 90 H. All accesses at addresses 8x H will generate a read back interrupt containing the addresses 80 H. Accesses at 9x H performs exactly the same thing that the 8X register except the interrupt will be at address 90 H. Response will be according to the role herebelow:
identification request: 1 0 0 Y X X X X X X X X X X X X identification response: 1 0 0 Y C C C C T T D D D D D D
with: - C = circuit revision (00000 for rev 2.x) - T = device type (U = 00) - D = device level identifying the manufacturer (001000 for SGS-THOMSON Microelectronics)
In particular for 2.X version the identification response is:
10 0Y0000 00001000
GENERAL PURPOSE I/Os (GCI) When GCI non-auto mode is selected, (NT or LT), four programmable I/Os (IO1, IO2, IO3, IO4) are provided and associated with CR5 register. Each I/O is internalIy pulled-up with a 50k resistor. Input or output can be selected for each pin independently from the others by means of bits IO1, IO2, IO3, IO4 in CR5. D1, D2, D3, D4 bits give the logical value of the I/O pins respectively. When a status change occurs on one of the input pins, CR5 is sent on the monitor channel of the GCI interface. When GCI auto-mode is selected, two inputs (ES1, ES2) and one output (EC) are provided in NT1-AUTO and NT-RRAUTO configurations only. ES1 and ES2 inputs drive the logical values of ps1 and ps2 bits in the M4 channel on the line while EC ouput normally high is driven low using the eoc message "operate 2B+D loopback. This intends to provide power supply testing command occuring simultaneously with the loopback command.
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TEST FUNCTIONS Various test functions are provided for transmitted pulse waveform checking, power spectral density measurement and transmitter linearity. Three commands in TXACT register are provided. The associated test function is enabled as long as the command is not disabled by any other command. SP1: (0010) Send Single Pulses+1, -1: +1, -1, pulses are transmitted consecutively onto the line, one pulse per frame. SP3: (1011) Send Single Pulses+3, -3: +3, -3, pulses are transmitted consecutively onto the line, one pulse per frame. RDT: (0011) Random Data Transmitted: Random data can be transmitted onto the line continously. B1, B2 and D channel transparency between the digital interface and the line is enabled. When auto-mode is selected, two test inputs (TEST1, TEST2) are provided allowing the same test functions as described above but without the need of a microcontroller. See Table 6 for Test pins biasing. Table 6: Test Pins
TEST1 1 1 0 0 TEST2 1 0 1 0 FUNCTIONS Normal operation Send Single Pulse 1 Random Data Transmitted Send Single Pulse 3
MONITOR channel depending of CID bit in CR2 register) is used in GCI mode. In MICROWIRE mode, a primitive indication generates first an interrupt requesting an action from the Microprocessor, in GCI mode the primitive Indication is directly transmitted via C/I (or MONITOR channel). Power on initialization Following the initial application of power, STLC5411 enters the power down deactivated state in MICROWIRE mode or in GCI mode depending on the polarization of the MW input. All the internal circuits including the master oscillator are inactive and in a low power state except for the 10 kHz Tone signal detector. The line outputs LO+/LO- are low impedance and all digital outputs are high impedance. All programmable registers and the activation controller are reset to their default value. GCI configuration is defined by means of the configuration pins M0, CONF1 and CONF2 when Power supply is turned on. For LT and NT1-2 equipments, GCI configuration should be completed by means of Control Register Programming. See Table 1 for configuration pins bias. Line activation request When UID is in the power down state and a 10kHz tone TN or TL is detected from the line. LSD and INT (MICROWIRE/DSI only) open drain outputs are forced to zero. In NT configuration , code LSD (0000) is loaded in the activation indication register RXACT. In LT configuration, code AP (1000) is loaded in the activation indication register RXACT. In Microwire/DSI these indications are sent onto CO at the following access even if the UID is still in power down mode. In GCI these indications are sent onto the C/I channel as soon as GCI clocks are available. LSD open drain output is set back in the high impedance state as soon as the UID is powered up. INT open drain output is set back in the high impedance state when CS input is detected at zero. Depending of the ACTAUT and PUPAUT bits in CR6 register, UID can powered up itself, also automatically to start the activation. For all auto mode configurations, on 10KHz tone reception, power up and activation procedure are full automatic, but in NT1 auto, UID waits the uoa bit from the line before to provide (or not) the cloks and primitives to the S device. Power up control Microwire/DSI: control instruction PUP in
TURNING ON AND OFF THE DEVICE STLC5411 contains an automatic sequencer for the complete control of the start-up activation sequences. Interactions with an external control unit requires only Activate Request and Deactivate Request commands, with the option of inserting break-points in the sequence for additional external control allowing for instance easy building of a repetor application. Automatic control of act, uoa/sai and dea bits in the M4 bit positions is provided, along with the specified 40 ms, 480 ms and 15 s timers used during the sequencing. Except the Power up and Power down control that is slightly different, the Activation/Deactivation procedures are identical in GCI and Microwire/DSI modes. Same command codes or indication codes are used. In Microwire and GCI mode, activation control is done by writing in the Activation Control Register TXACT and by reading the Activation Indication Register RXACT. For TXACT and RXACT access, MICROWIRE port is used in MICROWIRE mode and C/I channel (or
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register is required to power up the UID. GCI: when GCI "NT master of the clocks"configuration is selected, UID provides the GCI clocks needed for control channel transfer; PUP control instruction is provided to the UID by pulling low the Bx data input; STLC5411 then reacts sending GCI clocks. It is possible to operate an automatic power up of the UID when a wake up tone is detected from the line by connecting the LSD output directly to the Bx input. GCI: when NT1-2 or LT configuration is selected (M0 = 0), the UID is powered up after configuration setting by the PUP code (0000) on C/I Channel. Power down control A control instruction PDN in ACT register is required to power down the device after a period of activity. PDN forces directly the device to the low power state without sequencing through any of the de-activation states. It should therefore only be used after the UID has been put in the line deactivated state. PDN has no influence on the content of the internal registers, but immediately stops the output clocks when UID is in master mode and in W/DSI mode. In GCI mode, UID send first two times code DI(1111) on C/I channel before powering down at the end of the assigned GCI channel. The DI code purpose is similar to PDN code but power down state is entered only when the line is entirely deactivated (state H1 or J1). The DI command is recommended in GCI mode and in W/DSI mode. Power up state Power up transition enables all analog and digital circuitry, starts the crystal oscillator and internal clocks. The LSD output is in the high impedance state even if a tone is detected from the line. As for PDN, PUP has no influence on the content of the internal registers Power down state Following a period of activity in the power up state, the power down state may be re-entered as described above. Configuration Registers remain in their current state. PDN and DI have no influence on the content of the internal registers: it is then possible, for instance, after a normal deactivation procedure followed by a power down command, to power up again the device in order to operate directly a Warm Start procedure. ACTIVATION/DEACTIVATION SEQUENCING Activation/deactivation signals onto the line are in accordance with the activation/deactivation state matrix given in Appendix A.
CASE OF RESTRICTED ACTIVATION The standard specifies a mode where the U interface can be turned on without the need to activate the S/T interface provided this function is supported at both ends of the loop. In this condition Maintenance channel is available, typically for setting loop-backs in the NT for error rate testing and other diagnostics. When this mode is enabled, bit M47 on the line in LT to NT direction becomes the uoa bit. Setting UAR activation command in the LT chip will set uoa bit equal zero on the line. Detection of uoa bit equal zero by the NT will inhibit activation of the S/T interface. This results in SN3 signal in the NT to LT direction, which causes generation of UAI indication by the LT U device when superframe synchronized. If during restricted activation operation, a TE starts to try activate the S/T interface by sending info 1, the NT can pass this request to the LT via M47 bit, the sai bit. This bit is set equal one by writing AR command to the Activation Control Register. sai bit received equal one causes generation of an AP indication by the LT U device.
RESET OF ACTIVATION/DEACTIVATION STATE MACHINE When the device is either powered-up or down, a control instruction RES resets the activation controller ready for a cold start. That feature can be used if the far-end equipment fails to warm start, for example if the line card or NT has been replaced or if in a regenerator, the loss of synchronisation of the second section imply the reset of the first section for a further cold start. The configuration registers remain in their selected value. HARDWARE RESET When GCI configuration is selected, pin 26 acts as a logical hardware Reset. The device is entirely reset including activation/deactivation state machine and configuration registers. Configuration pins bias excluding MW define the eventual new configuration. Pin MW must be maintained at the 0 Volt for GCI configuration setting. It is possible to operate a similar "complete reset" of UID by setting high bit RST in the RXOH command register. In this last case the Control interface remains enabled. QUIET MODE It is possible to force the device in a quiet mode in which UID does not react to any line wake-up tone; LSD pin will remain high. There are two
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ways to enter quiet mode: QM bit in CR6 register and QM primitive command to write in TXACT register; in this last case, any further primitive will clear quiet mode. CR2 register). All commands and indications are coded on four bits: C1, C2, C3, C4. Codes are listed in Table 7. For each mode, a list of recognized commands and generated indications is given. Hereafter, you have a detailed description of the codes depending on mode selected. NT mode: Command 0000 (PUP): Power Up When in the power down state, PUP command powers up the device ready for a cold or a warm start. When GCI is selected with clocks as outputs, PUP command is replaced by pulling low Bx input pin. 0001 (RES): Reset RES command resets UID ready for a cold start. Configuration registers are not changed. RES can be operated when the device is either powered up or down. If RES command is applied when the line is not fully deactivated, UID properly ends the activation before to come back in H1 state; In this case DP or EIU indication is returned (Auto mode configuration or not respectively). 0010 (SP1): Send Single Pulse +1 and -1 SP1 test command forces UID to send +1, -1, pulses to the line, one pulse per frame. 0011 (RDT): Random Data Transmitted RDT test command forces UID to send data with random equiprobable levels at 80 kbaud. 0100 (EIS): Error Indicate S Interface EIS command reports on the U line, a default on the S interface. 0101 (PDN): Power Down PDN command forces UID to power down state. It should normally be used after UID has been set in a known deactivated state, e.g. in an NT after a DI status indication has been reported. In GCI, C/I indication (DI) is sent twice on Br output before UID powers down. 0110 (UAI): U interface Activation Indicate UAI command is significant only when RR bit is set equal one in CR2 register or if NT-RR-AUTO auto-mode is selected. After the receiver has been super-frame synchronized, UAI command allows UID to send SN3 signal to the line. 0111 (QM): Quiet Mode In this mode, UID does not react to any line status change. UID can be powered up or down and ready for a cold start or a warm start. All configuration registers and coefficients remain unchanged. Quiet Mode is disabled by any other command. Note: Inside UID, an logical or is implemented with this QM primitive and the QM bit in CR6 register. 1000 (AR): Activation Request Beeing in the Power Up and deactivated state
AUTOMODE For all auto mode configurations, AIS pin allows a choice of line interface: 27 or 15mH for the transformer and resistors line or device side. In NT1, the activation/deactivation state machine and the automatic power-up / power-down capabilities of the UID provide for a direct connection through GCI between UID and SID-GCI (ST 5421) without the need of an extra microcontroller (see figure 13b). LSD- pin of SID-GCI must be connected together to the Bx input pin of UID to ensure autonomous power-up/down control. Activation/Deactivation commands and indications are transferred from one device to the other by means of the C/I channel. Maintenance functions are automatically processed in UID. Therefore, there is not transfer of messages on the Monitor channel between UID and SID-GCI. Please note that the 2B+D loop-back request at the S interface is provided using the C/I channel code ARL and that there is not automatic processing of S and Q messages in SID-GCI. In Repetor, the same advantages provide for a direct connection through GCI between both UID without the need of an extra microcontroller (see figure 13c). As for NT1, C/I channel transfers activation/deactivation commands and indications. Maintenance functions are automatically processed in UIDs, needing the transfer of eoc messages, overhead bits and CRC fault detections. This is performed autonomously on the Monitor channel by sending when required messages in a regular format as already described.EOC messages are transmitted according to Table 5; overhead bits in the M4 channel excluding (act, dea, uoa and sai) transferred transparently; spare overhead bits in M5 or M6 bit positions are also transferred transparently; febe and nebe bits are transmitted according to Figure10.
COMMAND INDICATION (C/I) CODES Activation, deactivation and some special test functions can be initiated by the system by writing in TXACT register. Any status change of the on-chip state machine is indicated to the system by the UID by setting a new code in the RXACT register. When GCI is selected, TXACT and RXACT registers are normally associated with the C/I channel (it is possible to associate them with the MONITOR channel thank to the CID bit in
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Table 7a: RXACT (indication) and TXACT (command) codes
CODES C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NT (GCI or MW, NON AUTO-MODE) RXACT (indications) DP/LSD EIU - - EI - - - AP - - - AI - - DI TXACT (commands) PUP (1) RES SP1 RDT EI PDN - QM AR - - SP3 AI - AIL DI LT (GCI or MW, NON AUTO-MODE) RXACT (indications) - EIU - - EI - UAI - AP - - - AI - - DI TXACT (commands) PUP/DR RES SP1 RDT FA0 PDN UAR QM AR - ARL SP3 AI - - DI
Note: (1) ONLY IN SLAVE MODE IN MASTER. MODE, SET BXpin TO `0` TO HAVE THE SAME EFFECT THAN PUP.
CODES C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
NTRR (GCI or MW, NON AUTO-MODE) RXACT (indications) DP/LSD EIU - - EI - UAP - AP - - - AI - - DI TXACT (commands) PUP (1) RES SP1 RDT EI PDN UAI QM AR - - SP3 AI - - DI
LTRR (GCI or MW, NON AUTO-MODE) RXACT (indications) - EIU - - EI - UAI - AP - - - AI - - DI TXACT (commands) PUP/DR RES SP1 RDT FA0 PDN UAR QM AR - ARL SP3 AI - - DI
(1) ONLY IN SLAVE MODE.
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Table 7b: RXACT (indication) and TXACT (command) codes.
CODES C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NT1 (GCI ONLY, AUTO-MODE) RXACT (indications) DP/LSD - - - EI - - - AP - ARL - AI - - DI TXACT (commands) (1) RES SP1 RDT EI PDN - QM AR - - SP3 AI - AIL DI
(1) SET Bx PIN TO `0` IS EQUIVALENT TO A PUP COMMANDE
CODES C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
NTRR (GCI ONLY, AUTO-MODE) RXACT (indications) DP/LSD EIU - - EI - UAP - AP - ARL - AI - - DI TXACT (commands) (1) RES - - EI - UAI - AR - - - AI - - DI
LTRR (GCI ONLY, AUTO-MODE) RXACT (indications) (2) EIU - - EI - UAI - AP - - - AI - - DI TXACT (commands) PUP/DR RES - - FA0 - UAR - AR - ARL - AI - - DI
(1) SET Bx PIN TO `0` IS EQUIVALENT TO A PUP COMMANDE
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(H1), AR instruction forces UID through the appropriate sequence to activate the line by sending TN followed by SN1. Beeing in the U-only-active state (H8A), AR command forces the sai bit equal 1 to the line. Is intended to transfer to the network an activation attempt at the S/T interface. 1011 (SP3): Send Single Pulse +3 and -3 SP3 test command forces UID to send +3, -3 pulses to the line, one pulse per frame. 1100 (AI): Activation Indicate AI command forces act bit equal one in SN3 signal transmitted to the line. Is intended to reflect an activate state at the S/T interface. 1110 (AIL): Activation Indicate Loopback Identical to AI command. Ensure direct compatibility with status indications of SID-GCI. 1111 (DI): Deactivation Indicate The DI command allows the UID to automatically enter the power down state if the line is deactivated. DI command has no effect as long as the line is not deactivated (DI status indication reported). EI status indication reports that act bit has been detected equal zero. 0110 (UAP): U interface Activation pending Is significant only when RR bit in CR2 has been set equal one or if NT-RR-AUTO mode is selected. UAP reports that the receiver is superframe synchronized with uoa bit received equal zero. 1000 (AP): Activation Pending AP reports that the receiver is superframe synchronized with uoa bit received equal one . 1010 (ARL): Activation Request Loopback Is significant only when NT1-AUTO or NT-RRAUTO mode is selected. ARL reports that an eoc message has been received requiring to operate a local 2B+D loopback. When connected to SIDGCI in a NT1 or to UID in LT-RR-AUTO mode in a regenerator, 2B+D loopback command is therefore automatically provided. 1100 (AI): Activation Indication AI reports that UID is superframe synchronized with act and uoa bits received equal one. 1111 (DI): Deactivation Indication DI reports that UID has entered the deactivated state (H1).
NT mode: Status indication 0000 (DP/LSD): Deactivation pending / Line signal detected When in the deactivated state (H1) either powered up or down, LSD status indication is reported if TN wake-up tone is detected except if NT1 AUTO is selected; in this configuration, UID must check uoa bit before to send (or not) LSD. When in the superframe-synchronized states, DP status indication reports that the dea bit has been received equal zero from the line. UID enters in the receive reset state. When NT1-AUTO mode is selected, DP status indication is reported also when a transmission error has been detected on the loop. This is intended to ensure immediate deactivation of the S/T interface. 0001 (EIU): Error Indication User EIU status indication is reported in following cases: a. to acknowledge RES command. UID is deactivated, ready for a cold start. b. to report a Loss of signal for more then 480ms on the line. c. to report a Loss of synchronization for more than 480ms on the line. In this case, when NTRR-AUTO is selected, EIU is replaced by RES; d. to report that an expire of Timer 4 interrupt has reset UID ready for a cold start. When NT1-AUTO is selected, EIU is replaced by (DP) (except in case c.). 0100 (EI): Error Indication
LT mode: Command 0000 (PUP/DR): Power Up / Deactivation Request When in the power down state, PUP command powers up the device ready for a cold or a warm start. When in one of the superframe synchronized states, DR command forces dea bit on the line equal zero for four consecutive superframes before ceasing transmission. 0001 (RES): Reset RES command resets UID ready for a cold start. Configuration registers are not changed. RES can be operated when the device is either powered up or down. If RES command is applied when the line is not fully deactivated, UID returns EIU indication and goes in J1 state (Receive Reset). If RES command is applied when the line is not fully deactivated, UID properly ends the activation before to come back in J1 state; in this case EIU indication is returned. 0010 (SP1): Send Single Pulse +1 and-1 SP1 test command forces UID to send +1, -1, pulses to the line, one pulse per frame. 0011 (RDT): Random Data Transmitted RDT test command forces UID to send data with random equiprobable levels at 80 kbaud. 0100 (FA0): Force act bit to Zero FA0 command forces the act bit to 0 in the SL3 signal transmitted to the line. Is intended to reflect a transmission failure detected on the network side of the loop relative to UID.
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0101 (PDN): Power Down PDN command forces UID to power down state. It should normally be used after UID has been set in a known deactivated state, e.g. in an LT after a DI status indication has been reported. In GCI, C/I indication DI is sent twice on Br output before UID powers down. 0110 (UAR): U-interface-only Activation Request Being Power Up and deactivated , UAR command forces UID through the appropriate sequence to activate the loop without activating the S/T interface. SL2/SL3 signal is sent with uoa bit set to zero. With the line already active, UAR command forces bit uoa equal zero: this is intended to deactivate the S/T interface. 0111 (QM): Quiet Mode This command has the same effect as in NT mode. 1000 (AR): Activation Request Being Power Up and deactivated, AR instruction forces UID through the appropriate sequence to activate the line by sending TL followed by SL1. SL2/SL3 signal is sent with uoa bit equal one. Beeing in the U-only-active states, AR command forces the uoa bit equal 1 to the line. Is intended to activate the S/T interface. 1010 (ARL): Activation Request with Loopback ARL test command forces UID through the appropriate sequence to activate with the complete transmit data stream looped-back to the receiver. When this loop-back is disabled by DR command, UID is ready to operate a warm start if a new ARL command is issued. 1011 (SP3): Send Single Pulse +3, -3 SP3 test command forces UID to send +3, -3 pulses to the line, one pulse per frame. 1100 (AI): Activation Indicate AI is an optional command recognized only when BP2 bit in CR2 register is set equal one or LTRR-AUTO mode is selected. Beeing in the superframe-synchronized state with act bit received from the line equal one, AI command allows UID to send act bit equal one to the line. 1111 (DI): Deactivation Indicate The DI command allows the UID to automatically enter the power down state if the line is deactivated. DI command has no effect as long as the line is not deactivated (DI status indication reported). LT mode: Status indication 0001 (EIU): Error Indication Interface U EIU status indication reports an error at U interface. It can be a `loss at signal` a `loss of sync`,`expiry of Timer 4 lias reset UID for coldstart` and `UID put in receive reset state by RES command`. 0100 (EI): Error Indication EI status indication reports that act bit has been
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detected equal zero. 0110 (UAI): U interface Activation Indication UAI reports that the line is superframe synchronized. 1000 (AP): Activation Pending Being in one of the deactivated states, AP reports that a wake up tone has been detected from the line. Beeing in the U-only-activated state, AP reports that sai bit has been detected equal one from the line. Is intended to reflect an activation attempt at the S/T interface. 1100 (AI): Activation Indication AI reports that UID is superframe synchronized with act bit received equal one. TE side of the loop relative to the UID is active 1111 (DI): Deactivation Indication DI reports that UID has entered the deactivated state (J1). B1, B2 and D channels transparency UID is able to control automatically transparency of B1, B2 and D channels. Nevertheless, when ETC bit in CR2 register is set equal 1, transparency is forced as soon as the line is synchronized. It is also possible to control each data channel B1, B2, D enabling at the DSI/GCI interface independently by means of bits EB1, EB2 and ED in CR4 register; Set equal 1, B1, B2 or D channel on the DSI/GCI interface is enabled; In this case, out of the transparency state (s), ones are forced on thee relevant time slot of the DSI/GCI, and ones or zeros are transmitted on the line conforming T1E1 recommendations. Set equal 0, relevant time slot on DSI/GCI is always in high impedance state and ones or zeros are transmitted on the line. In this last case, as soon as transparency is enabled, ones are transmitted to the line. When RDT test command is applied, transparency on 2B+D is forced. This intend to permit the user, if required, to send a random sequence of bits to the line. Please note that the on-chip scrambler normally ensures transmission of equiprobable levels to the line, even if logical one only is provided to the DSI/GCI system interface. INTERNAL REGISTERS DESCRIPTION. Here following a detailed description of STLC5411 internal registers. Internal registers can be accessed: a) In GCI mode, according to the monitor channel exchange rules. For RXACT and TXACT also through C/I channel. b) in W/DSI mode, using the MICROWIRE interface according to the rules described in section "W control interface". Table 8 gives the list of all the STLC5411 internal registers can be used in MICROWIRE mode. Table 9 gives the list of all the STLC5411 internal registers can be used in GCI mode. Registers are grouped by types and address ar-
STLC5411
eas: area 00/0FH: NOP operations. area 10/1FH: test registers: reserved. area 20/2FH: the configuration registers. OPR CR1 CR2 CR3 CR4 CR5 CR6 Read Write access. CR5 only usefull in GCI mode area 30/3FH: the B1 B2 D time slot registers. TXB1 TXB2 RXB1 RXB2 TXD RXD STATUS Read Write access except STATUS: Read only. Usefull only in MW mode except STATUS: MW & GCI modes. area 40/4FH: the transmit and receive registers (except EOC). TXM4 RXM4 TXM56 RXM56 TXACT RXACT BEC1 BEC2 ECT1 ECT2 RXOH Read Write access for the transmit registers: TXM4 TXM56 TXACT Read access only for the receive registers: RXM4 RXM56 RXACT Read Write access for the control registers: ECT1 ECT2 Read access only for the error registers: BEC1 BEC2 Write access only for the command registers: RXOH area 5x to 9x: for 12 bits registers. to write TXEOC register, to read 5x: RXEOC register. to read TXEOC register. 6x: reserved 7x: 8x & 9x: to read IDR register. area Ax to Ex: reserved. reserved except FF address: area Fx: special register MWPS. Overhead bits programmable register (OPR) After reset: 1EH
CIE EIE FIE OB1 OB0 OC1 OC0 C2E
CIE = 1: the RXM56 register is queued in the interrupt register stack with nebe bit set to zero each time the CRC result is not identical to the corresponding CRC received from the line. CIE = 0: no interrupt is issued but the error detection remains active for instance for on chip error counting. EIE Error counting Interrupt Enable: EIE = 1: an interrupt is provided for the counter when the threshold (ETC1 or ETC2) is reached. EIE= 0: no interrupt is issued. It is feasible to read the counters even if no relevant interrupt has been provided. FIE FEBE lnterrupt Enable: FIE = 1: the RXM56 register is queued into the interrupt register stack each time the febe bit is received at zero in a superframe. no interrupt is issued but the receive febe bit remains active for on chip error counting.
FIE = 0:
OB1, OB0 Overhead Bit processing: select how each spare overhead bit received from the line is validated and transmitted to the system. RXM4 and RXM56 registers are independently provided onto the system interface as for the eoc channel. Each spare overhead bit is validated independently from the others. OB1 0 OB0 0 each super frame, an interrupt is generated for the RXM4 or the RXM56 register. Spare bits are transparently transmited to the system. an interrupt is set at each new spare overhead bit(s) received. an interrupt is set at each new spare overhead bit(s) received and confirmed once. ( two times identical). an interrupt is set at each new spare overhead bit(s) received and confirmed twice. (three times identical).
0 1
1 0
1
1
CIE Near-End CRC Interrupt Enable:
If new bits are received at the same time in M4
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and M56, both registers RXM4 and RXM56 are queued in the interrupt register stack. Bits act, dea, uoa, sai are dedicated to the activation procedure. Validation is always done in accordance with the ANSI rule: validation at each new activation bit received and confirmed twice independently from the above rules. These bits are taken into account directly by the activation decoder. An interrupt is not generated for the RXM4 Register when one of these bits changes, but they are provided for test to the RXM4 Register. OC1, OC0 eoc channel processing: select how a received eoc message is validated and transmitted to the system. OC1 0 OC0 0 every half a super frame, an interrupt is generated for the RXEOC register. eoc channel is transparently transmitted to the system. an interrupt is set at each new eoc message received. an interrupt is set at each new eoc message received and confirmed once. (two times identical) an interrupt is set at each new eoc message received and confirmed twice. (three times identical). only) CK0-CK2 bits select the BCLK output frequency when DSI clocks are outputs. CK2 0 0 0 0 1 CK1 0 0 1 1 0 CK0 0 1 0 1 0 BCLK frequency: 256KHz 512KHz 1536KHz 2048KHz 2560KHz
DDM Delayed Data Mode select:(W/DSI only) Two different phase-relations may be established between the Frame Sync signals and the first bit of the frame on the Digital Interface: DDM = 0: Non delayed data mode The first bit of the frame begins nominally coincident with the rising edge of FSA/B. DDM = 1: delayed data mode: FSA/B input must be set high at least a half cycle of BCLK earlier the frame beginning. CMS Clocks Master Select:(W/DSI only) CMS = 0: BCLK, FSA and FSB are inputs; BCLK can have in Format 1, 2 and 3 value between 256KHz to 4096KHz, value in Format 4: 512KHz to 6176KHz. CMS = 1: BCLK, FSA and FSB are outputs; FSA is a 8 kHz clock pulse indicating the frame beginning, FSB is a 8 kHz clock pulse is indicating the second 8 bits wide time-slot. BCLK is a bit clock signal whose frequency bits CK2-CK0. BEX B channels Exchange: BEX = 0: B1 and B2 Tx/Rx channels are associated with TXB1/RXB1 and TXB2/RXB2 registers respectively. BEX = 1: B1 and B2 channels are exchanged. Configuration register 2 (CR2) After reset: W mode 00H GCI: MO = 0 (LT/NT12) = 00H GCI: MO = 1 (NT/TE) = 80H W (LT,NT):
SFS NTS DMO DEN ETC BP1 EIF BP2 BFH9D RR
0 1
1 0
1
1
C2E Counter 2 enable: C2E = 0: Only counter BEC1 is used for both febe and nebe counting. C2E = 1: Counter BEC1 is used for nebe. Counter BEC2 is used for febe. Configuration register 1 (CR1) After reset: W mode 00H GCI: MO = 0 (LT/NT12) = C0H GCI: MO = 1 (NT/TE) = D2H
FF1 FF0 CK2 CK1 CK0 DDM CMS BEX
FF1, FF0 Frame Format Selection: (W/DSI only) Refer to fig. 2 and 3. FF1 0 0 1 1 FF2 0 1 0 1 Format 1 Format 2 Format 3
Format 4
GCI (LT,NT):
SFS NTS T24D CID ETC BP1 EIF BP2 BFH9D RR
SFS Super Frame Synchronization Select: Significant in LT mode only.
CK0-CK2 Digital Interface Clock select: (mW/DSI
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SFS = 0: SFSx is an input that synchronizes the transmit superframe. SFS = 1: SFSx is an output indicating the Transmit Superframe. In NT mode SFSx is always an output. NTS LT / NT mode Select. NTS = 0: LT mode selected NTS = 1: NT mode selected DMO D channel Transfer mode Select.(W/DSI only) Significant only when DEN=1. DMO = 1: D channel data is shifted in and out on Dx and Dr pins in continuous mode at 16 kbit/s on the falling and rising edges of DCLK respectively. DMO = 0: D channel data is shifted in and out on Dx and Dr pins in a TDM mode at the BCLK frequency on the falling and rising edges of BCLK respectively when the assigned time-slots are active. T24D: 24ms timer desable (GCI only). T24D = 1: The timer watches at the exchange on MONITOR channel every time the UID sends new byte. If it expires before pre-acknoledgement, an abort message is generated; In this last case, the aborted message is lost. T24D = 0: The timer is desable. This means for instance that UID may wait an preacknoledgement for ever. DEN D channel port Enable. (W/DSI only) DEN = 0: D channel port disabled. D bits are transferred on Br and Bx; Multiplexed mode is selected automatically. DEN = 1: D channel port (DX, DR, and DCLK when DMO bit equal 1) is selected. D bits are transferred on Dr and Dx in a mode depending on DMO bit setting. CID: C/I channel desable (GCI only). CID = 0: TXACT and RXACT registers only accessible via the C/I channel. Others registers only accessible via MONITOR channel. CID = 1: All registers only accessible via the MONITOR channel. ETC 2B+D Data Extended Transparency channel. ETC = 1: 2B+D channel transparency is enabled as soon as the line is superframe synchronized. ETC = 0: 2B+D channel transparency is under control of the on-chip state machine: act bit equal one both directions. BP1 Break Point 1 during activation(significative only when NTS = 0: LT mode) . BP1 = 1: During an activation attempt from the loop, (before SL2 sending) UID waits for an AR command to pursue activation. It is recommended to set BP1 equal 1 for repetor application. BP1 = 0: The activation procedure is automatically processed without the need of an AR command. EIF Error Indication Filter. Significant in NT mode only EIF = 0: act bit is set to zero in the transmit superframe in case of EI command, even if EI is sent sporadically. EIF = 1: act bit may be not set to zero in the transmit superframe in case of EI command with a duration of less than 36ms. BP2 Break Point 2 during activation. Significant only when NTS=0 (LT selected) BP2 = 1: During a full activation procedure, UID receiving act bit set to one in the received SN3 signal, UID waits for an AI command to send act bit equal one in SL3 signal. It is recommended to set BP2 equal 1 for repetor application. BP2 = 0: The activation procedure described above is automatically processed without the need of an AI command. BFH9D: Back from H9 disabled. (Significant in NT mode only) BFH9D = 0: UID is in H9 state (pending deactivation) after reception of dea bit = 0. It is waiting a loss of signal to return in H1 state via H12. BFH9D = 1: UID is H9 state (pending deactivation) after reception of dea bit = 0. It is waiting a loss of signal to return in H1 state via H12, or dea bit = 1; In this last case UID returns in the previous state. RR Repetor mode. RR = 0: UID activation/deactivation complies with the standard requirements for NT1 or LT equipment depending on NTS bit select. See state matrix for the detailed behaviour of UID.
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RR = 1: UID activation/deactivation complies with the requirements for repetor equipment. "LT" or "NT" behaviour is selected by means of bit NTS. BP1 and BP2 break-points should be set equal one too. See state matrix for the detailed behaviour of UID in this mode of operation. Configuration register 3 (CR3) After reset: 00H
LB1 LB2 LBD DB1 DB2 DBD TLB T15D
Configuration register 4 (CR4) After reset: E0H
EB1 EB2 ED FFIT ESFr CTLIO MOB CTC
EB1 B1 channel Enabling EB1 = 1: Selected B1 channel time-slot on the DSI/GCI interface is enabled. Note that transparency of B1 channel remains under control of the activation state machine and the ETC bit in CR2. EB1 = 0: Selected B1 channel time-slot on the DSI/GCI interface is disabled: Br output remains in high impedance state and data on Bx input is ignored. Ones (NT) or zeroes (LT) are transmitted on the line. EB2 B2 channel Enabling Identical to EB1 bit but for B2 channel. ED D channel enabling identical to EB1 but for D channel on Bx/Br pin or DX/Dr pin depending on DEN bit in CR2 register. FFIT FIFOs interrupt. FFIT = 1: overflow or underflow of the TXFIFO and RXFIFO are reported in STATUS register. An interrupt is generated in MW mode, a MONITOR message is automatically sent in GCI mode. FFIT = 0: No interrupt or message is generated when FIFOs overflow or underflow. ESFr Enable SFSr on pin25 ESFr = 0: LSD open drain output is selected on pin 25. ESFr = 1: SFSr output is selected on pin 25. CTLIO Control IO (significant in GCI mode only) CTLIO = 1: The input pins configurated via CR5 register generate a message on every change even if the UID is powered down in master mode; that is to say UID is able to wake up itself, to provide the clocks, to sends the message. After that UID is automatically powered down except if a PUP command is sent to it. CTLIO = 0: In master mode and powered down, the UID does not react to a input pin change. MOB Mask Overhead Bits. MOB = 0: No Mask on overhead bit interrupts.
LB1, LB2, LBD Line side Loopback select. When set high they turn each individual B1, B2, or D channel from the Line receive input to the Line transmit output. They may be set separately or together. The loopback is operated close to Bx and Br (or Dx and Dr if the D port is selected). These loop backs ensures channels integrity. DB1, DB2, DBD Digital side Channel Loopback select. When set high they turn each individual B1, B2, or D channel from the Digital Interface receive input to the Digital Interface transmit output. They may be set separately or together. The loopback is operated close to Bx and Br (or Dx and Dr if D port selected). These loop backs ensures channels integrity whatever the selected format or assigned channels time slot. TLB Transparent Loopback select TLB = 0: Digital loopbacks are non transparent. When line side loopback is set, data transmitted onto the digital interface is forced to one. When digital side loopback is set, data transmitted onto the line is forced to 1 in NT mode and to 0 in LT mode. TLB = 1: 2B+D is transparently transferred through the UID. T15D Timer 15 second disabled T15D = 0: On-chip 15 second timer (timer 4 or 5 of ANSI standard) is enabled and ensure full reset of the activation procedure in case of non synchronization of the line within 15 second. T15D = 1: On-chip 15 second timer is disabled. This means for instance that UID may attempt to synchronize for ever.
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MOB = 1: All interrupts issued from RXM4, RXM56 RXEOC and CR5 are masked. It is still possible to read these registers via RXOH. CTC Corrupted Transmit CRC Control CTC = 0: Allows the normal calculation of the CRC for the transmitted data to the line. CTC = 1: The CRC result transmitted to the line in the next Superframe is inverted. This ensure transmission of corrupted CRC as long as CTC equal 1. Configuration Register 5 (CR5) Significant in GCI only. After reset: FFH
IO4 IO3 IO2 IO1 D4 D3 D2 D1
ACTAUT: Activation Automatic ACTAUT = 1: If UID is powered up, a 10KHz tone from the line starts the activation without need of extra commands (like AR), except when QM (Quiet mode) is enterred. ACTAUT = 0 A detection of a 10KHz tone from the line does not start the activation: UID waits a primitive command (normaly AR). PUPAUT PUP Automatic PUPAUT = 1: If UID is powered up, a 10KHz tone from the line allows an automatic power up of the UID. Notes if ACTAUT is set to 1, from a power down state a 10KHz tone automatically starts the activation. PUPAUT = 0: A detection of a 10KHz tone from the line does not power up the device: UID waits a PUP primitive command. QM Quiet mode. QM = 1: has the same effect of the QM primitive command enterred in TXACT register. An or logic is done with the QM bit and the QM primitive. The goal of this bit is to allow a quiet mode for an UID in power down state in some applications. QM = 0: no effect. AIS Analog Interface Select. AIS = 1: selects an analog interface using 27mh transformer. AIS = 0: selects an analog interface using 15mh transformer TFB0 Transmit febe equal 0
IO4, IO3, IO2, IO1 Input/Output select for I/O pins (14, 15, 16, 18) IOi = 1: IOi pin is selected as an input. An onchip pull up resistor ensures a stable logical 1 at power-on reset or if IOi pin is not connected to stable source. IOi = 0: IOi pin is selected as an output. Each I/O pin can be selected independentlyfrom the others. D4, D3, D2, D1 I/O pin logical level command/status. D4, D3, D2, D1 bits are associated with IO4, IO3, IO2, IO1 pins respectively. When IOi pin is selected as an output, the associated Di bit can be written to control the logical level of the output; Di equals 1 commands a high level on IOi. When IOi pin is selected as an input, the associated Di bit indicates the status of the input; Di equals one indicates a high level on IOi. CR5 register is buffered in the interrupt stack each time a status change is detected on an input. It is also possible to read-back at any time CR5. Configuration register 6 (CR6) After reset: 0FH
T15E ACTAUT PUPAUT QM AIS TFB0 RFS LFS
T15E Timer 15 seconds extension T15E = 0: The on chip T4 or T6 timer is done for the ANSI standard: 15 seconds. T15E = 1: The on chip T4 or T5 timer is extended to 20 seconds. Note: the T15D bit in CR3 register enables or desables the T4/T5 timer independently of theT15E bit.
TFB0 = 0: A permanent febe bit = 0 is sent on the line as long as TFB0 = 0 TFB0 = 1: The febe bit sent on the line is normaly computed.
RFS Remote febe select. Please report to the figure 10. RFS is usefull in report application to transfert or not the anomalies
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second line section to the first line section and viceversa. RFS = 1: Transfert anomalies second section first section and viceversa allowed. RFS = 0: Transfert anomalies second section first section and viceversa not allowed. LFS Local febe select. Please report to the figure 10. LFS is usefull in report application to transfert or not the crc anomalies (nebe) of a line section to the febe bit of the same line section. RFS = 0: The computing febe takes in account the local nebe. RFS = 1: The computing febe does not take in account the local nebe. Configuration register TXB1 Significant only when format 3 selected. (W/DSI Only) After reset: 00H Time slot 0 selected.
B1X5 B1X4 B1X3 B1X2 B1X1 B1X0
are numbered from 0 to 63. The register content is taken into account at each frame beginning. Configuration register RXB2 Significant only when format 3 selected. (W/DSI Only) After reset: 01H Time slot 1 selected.
B2R5 B2R4 B2R3 B2R2 B2R1 B2R0
B2R5-B2R0 Receive B2 Time Slot Assignment Those bits define the binary number of the receive B2 channel time-slot on BR output. Time slot are numbered from 0 to 63. The register content is taken into account at each frame beginning. Configuration register TXD After reset: W mode 08H (sub time slot 0, time slot 2 selected) Significant only when format 3 is selected with the D channel selected in the multiplexed mode:
DX5 DX4 DX3 DX2 DX1 DX0 SX1 SX0
B1X5-B1X0 Transmit B1 Time Slot Assignment Those bits define the binary number of the transmit B1 channel time-slot on Bx input. Time slot are numbered from 0 to 63. The register content is taken into account at each frame beginning. Configuration register RXB1 Significant only when format 3 selected. (W/DSI Only) After reset: 00h Time slot 0 selected.
- - B1R5 B2R4 B2R3 B2R2 B2R1 B2R0
DX5-SX0 Transmit D channel Time Slot Assignment DX5-DX0 and SX1-SX0 bits define the binary number of the transmit D channel time-slot. DX5DX0 bits define the binary number of the 8 bits wide timeslot. Time slot are numbered from 0 to 63. Within this selected time slot, SX1,SX0 bits define the binary number of the 2 bits wide timeslot. Sub time-slots are numbered 0 to 3. The register content is taken into account at each frame beginning. Configuration register RXD After reset: W mode 08H (sub time slot 0, time slot 2 selected) Significant only when format 3 is selected with the D channel selected in multiplexed mode.
DR5 DR4 DR3 DR3 DR2 DR1 SR1 SR0
B1R5-B1R0 Receive B1 Time Slot Assignment B1R5-B1R0 bits define the binary number of the receive B1 channel time-slot on BR output. Time slot are numbered from 0 to 63. The register content is taken into account at each frame beginning. Configuration register TXB2 Significant only when format 3 selected. (W/DSI Only) After reset: 01H Time slot 1 selected.
B2X5 B2X4 B2X3 B2X2 B2X1 B2X0
B2X5-B2X0 Transmit B2 Time Slot Assignment Those bits define the binary number of the transmit B2 channel time-slot on Bx input. Time slots
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DR5-SR0 Receive D channel Time Slot Assignment DR5-DR0 and SR1-SR0 bits define the binary number of the receive D channel time-slot. DR5DR0 bits define the binary number of the 8 bits wide timeslot. Time slot are numbered from 0 to 63. Within this selected time slot., SR1,SR0 bits define the binary number of the 2 bits wide timeslot. Sub time-slots are numbered 0 to 3. The register content is taken into account at each frame beginning.
STLC5411
Status Register (STATUS) (Read only) After reset: 85H
PWDN X X X RXFFU RXFFO TXFFU TXFFO
PWDN Power down PWDN = 1: UID is in power down state PWDN = 0: UID is in power up state RXFFU RX FIFO underflow RXFFU = 1: The bits rate on Br pin is higher than the bits rate side line. RXFFU = 0: The bits rate on Br is in accordance with the bits rate side line RXFFO: RX FIFO overflow RXFFO = 1:The bits rate on Br pin is lower than the bits rate side line. RXFFO = 0:The bits rate on Br pin is in accordance with the bits rate side line. TXFFU TX FIFO underflow TXFFU = 1: The bits rate on Bx pin is lower than the bits rate side line. TXFFU = 0: The bits rate on Bx pin is in accordance with the bits rate side line. TXFFO Tx FIFO overflow TXFFO = 1: The bits rate on Bx pin is higher than the bits rate side line. TXFFO The bits rate on Bx pin is in accordance with the bits rate side line. When one of these four bits is set to 1, Tx FIFO and/or Rx FIFO is re-adjusted and data is lost. An interrupt or message is generated if FFIT bit in CR4 register is set to 1. It is always possible to read this register by writting STATUS bit = 1 in RXOH register. Transmit M4 channel register (TXM4) After reset: 7DH
m42X m43X m44X m45X m46X m48X
bits in the TXM4 register are not significant. m45X in NT mode is CS0 bit: this is normally 0 (UID performing warm start). Nevertheless, user can force CSO to 1 by setting m45X to 1. When a read back is operated on TXM4, m41x, m42x in LT, m47x are indicating the current value of act, dea in LT and uoa/sai bits transmitted to the line. Receive spare M4 overhead bits register (RXM4) (read only) After reset: 75H
m41r m42r m43r m44r m45r m46r m47r m48r
RXM4 Register is constituted of 8 bits. When the line is fully activated (super frame synchronized), STLC5411 extracts the M4 channel bits. m41 is the act bit; m42 in NT mode is the dea bit; in NT m47 is the uoa bit; in LT m47 is the sai bit. These bits are under the control of the activation sequencer. No interrupt cycle is provided for the RXM4 register when a change on one of the activation bits is detected; never the less, they are available in RXM4. When one of the remaining received spare bits is validated following the criteria selected in the Configuration Register OPR, the RXM4 register content is queued in the interrupt register stack, if no mask overhead bits is set (see MOB bit in CR4 register). It is always possible to read this register by writting RXM4 bit = 1 in RXOH register. Transmit M5 and M6 (TXM56) After reset: 1FH
-
channels register
m51X m61X m52X
febx
febx
When transmitting SL2/SL3 or SN3, the UID shall continuously send in the M4 channel field the register content to the line once per superframe. Register content is transmitted to the line at each superframe. m41X, m42X in LT, m47X are activation bits. These bits are controlled directly by the on chip activation encoder-decoder. The corresponding
m51X, m61X, m52X spare over-head bits are normally equal to 1. Default value can be changed by setting the respective bits. These bits are transmitted to the line in SL2/SL3 or SN3 signal. febx Transmit febe bit control The febe can be forced to 0 by writing 0 in one of febx if RFS bit in CR6 register is set to 1. The febe bit set to zero is sent once to the line in the following available superframe. After febe transmission, febx bit returns to 1; the two bits positions are identical and allow direct compatibility between UIDs set in auto-mode (repeter). Note: the febx bits in TXM56 register are not the only way to force febe = 0 to the line. First, the febx action is controlled by RFS bit in CR6 register. Second, the nebe = 0 (local crc cmputing result) forces also febe = 0 to the line and this action is controlled by LFS bit in CR6 register. Third, TFB0 = 0 in CR6 register forces permanentely febe = 0 to the line.
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Receive M5 and M6 overhead bits register (RXM56) (read only) After reset: 1FH
m51r m61r m52r febr nebr
Block Error counter 1 (BEC1) (read only) After reset: 00H
ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0
When the line is fully activated (super frame synchronized), STLC5411 extracts the overhead bits. When one of the received spare bits m51, m61, m52 is validated following the criterias selected in the Configuration Register OPR. The RXM56 register content is queued in the interrupt register stack, if no mask overhead bits is set (see MOB bit in CR4 register). If the FIE bit in OPR register is set high, the RXM56 register content is queued in the interrupt register stack each time the febe bit is received equal zero with bit feb equal 0. The CRC received from the far-end is compared at the end of the superframe with the CRC calculated by the UID during that superframe. If an error is detected, the febe bit in the transmit direction is forced equal zero in the next superframe. If the CIE bit in the OPR register is set high, the RXM56 register is queued in the interrupt register stack at each CRC error detected with bit neb equal zero. It is always possible to read this register by writing RXM56 bit = 1 in RXOH register.
This Register indicates the binary value of the Block Error up-counter 1. Error are counted according to C2E bit setting in register OPR (nebe + febe or nebe only). When counter one reachs the threshold ECT1, BEC1 register is queued in the interrupt stack. BEC1 is reset to zero when it is read. Block Error counter 2 (BEC2) (read only) After reset: 00H
ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0
This Register indicates the binary value of the Block Error up-counter 2. Febe errors are always counted. According to C2E bit setting in register OPR, when counter one reachs the threshold ECT2, BEC2 register is queued in the interrupt stack. BEC2 is reset to zero when it is read. Threshold Block Error Counter 1 register (ECT1) After reset: FFH
Activation control register (TXACT) After reset: 0FH
C4 C3 C2 C1
ect17
ect16
ect15
ect14
ect13
ect12
ect11
This register is constituted of four bits: (C1, C2, C3, C4). In GCI mode, this register is normaly addressed by means of the C/I channel, but it is possible to address it by means of the MONITOR channel (see CID bit in CR2 register).
It is possible to load in this register the binary value of a threshold for the Block Error counter 1.When Block error counter reachs this value, an Interrupt relative to BEC1 register is loaded in the interrupt stack. This can be used as an early alarm in case of degraded transmission. Threshold Block Error Counter 2 register (ECT2) After reset: FFH
Activation indication register (RXACT) (read only) After reset: 0FH
C4r C3r C2r C1r
ect27
ect26
ect25
ect24
ect23
ect22
ect21
This Register is constituted of four bits: (C1r, C2r, C3r, C4r). At each activation status change, RXACT is queued in the interrupt register stack. In GCI mode, the C1-C4 bits are directly sent on the C/I channel or monitor channel depending on the CID bit in CR2 register. Activation Indication instructions are coded on 4 bits according to activation control description. It is always possible to read this register by writting RXACT bit = 1 in RXOH register.
It is possible to load in this register the binary value of a threshold for the Block Error counter 2.When Block error counter reachs this value, an interrupt relative to BEC2 register is loaded in the interrupt stack. This can be used as an early alarm in case of degraded transmission. Receive status register - read command (RXOH) (Write only)
EOC M4 M56 ACT 0 STATUS 0 RST
Reset to zero of all the RXOH bits is automatic.
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EOC Receive EOC status register read. When EOC bit is set equal one, UID automatically loads the current value of RXEOC register in the interrupt stack independently of any status change. M4 Receive M4 overhead bits status register read. When M4 bit is set equal one, UID automatically loads the current value of RXM4 register in the interrupt stack independently of any status change. M56 Receive M5 and M6 overhead bits status register read. When M56 bit is set equal one, UID automatically loads the current value of RXM56 register in the interrupt stack independently of any status change. ACT Activation indication status. When ACT bit is set equal one, UID automatically loads the current value of RXACT register in the interrupt stack independently of any status change. In GCI mode, the RXACT read back always uses the monitor channel. STATUS When STATUS bit is set egal one, UID automatically loads the current value of STATUS register in the interrupt stack independently of any status change. RST RESET (MICROWIRE/DSI configuration only). When RST bit is set equal one, UID is fully reset including configuration registers, state machine and all coefficients and reset to their default value. UID enters in the power-down state. address (EFG), 1 bit data/message Flag (H), 8 bits information (XEOC1 - XEOC8). When transmitting SL2/SL3 or SN3 signal. STLC5411 shall continuously send into the EOC channel field the eoc bits twice per superframe. TXEOC register is loaded in the transmit register at each half a superframe. The address of this register is composed only of 4 bits. Read-back can be performed by means of a read-back command 6100H. Receive EOC register (RXEOC) (read only) After reset: FFFH
REOC1 REOC2 REOC3 REOC4 REOC5 REOC6 REOC7 REOC8
The RX EOC Register is constituted of 12 bits. When the line is fully activated (super frame synchronized) and when a new eoc message is received and validated in accordance with the criteria selected in the Configuration Register OPR, the RX EOC Register is queued in the interrupt register stack. The address of this register is composed only of 4 bits. It is always possible to read this register by writing RXEOC = 1 in RXOH register Identification Register (IDR) Fixed value: 08H (read only) When a read-back operation of IDR register is entered, UID loads the Identification Register in the interrupt stack. This register provides a reserved identification code agreed by GCI standard: 08H. IDR register is accessible via two addresses. MWPS Micro Wire Port Select register (Significant in microwire mode only). (write only) Default value: Mode A (5410 compatible) - Writting FFH value select the mode B to exchange data onto CI & CO - Writing 00H value select the mode A (See Microwire control interface paragraph for more details Mode A, Mode B). Note: Soft Reset has no effect on the select mode.
Transmit EOC register (TXEOC) After reset: FFFH
XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8
TXEOC Register is constituted of 12 bits, 3 bits
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Table 8: REGISTER ACCESS MESSAGES
FUNCTION NOP RESERVED OPR OPR CR1 CR1 CR2 CR2 CR3 CR3 CR4 CR4 CR5 CR5 CR6 CR6 RESERVED TXB1 TXB1 TXB2 TXB2 RXB1 RXB1 RXB2 RXB2 TXD TXD RXD RXD RESERVED
Notes: 1. Bit 7 of byte 1 is the first bit clocked into the UID. 2. All configuration registers can be read-back by setting bit 7 of BYTE 1 equal 1 3. RXOH is a Write only register to force RXEOC, RXM4, RXM56, RXACT status register sending. RST reset the device 4. It is recommended not to access all RESERVED adresses. X means 1 or 0 W refers to a write operation. R refers to a request for read-back.
BYTE 1 AD7/4 0000 0001 W R W R W R W R W R W R W R W R W R W R W R W R W R 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 AD3/1 000 XXX 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 000 000 001 001 010 010 011 011 100 100 101 101 11X AD0 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X 7 0 0 CIE 0 FF1 0 SFS 0 LB1 0 EB1 0 IO4 0 T15E 0 0 0 0 0 0 0 0 0 0 DX5 0 DR5 0 0 6 0 0 EIE 0 FF0 0 NTS 0 LB2 0 EB2 0 IO3 0 0 0 0 0 0 0 0 0 0 0 DX4 0 DR4 0 0 5 0 0 FIE 0 CK2 0 DMO 0 LBD 0 ED 0 IO2 0 0 0 B1X5 0 B2X5 0 B1R5 0 B2R5 0 DX3 0 DR3 0 0
BYTE 2 4 0 0 OB1 0 CK1 0 DEN 0 DB1 0 FFIT 0 IO1 0 QM 0 0 B1X4 0 B2X4 0 B1R4 0 B2R4 0 DX2 0 DR2 0 0 3 0 0 OB0 0 CK0 0 DD 0 DB2 0 ESFr 0 D4 0 AIS 0 0 B1X3 0 B2X3 0 B1R3 0 B2R3 0 DX1 0 DR1 0 0 2 0 0 0C1 0 DDM 0 BP1 0 DBD 0 CTLIO 0 D3 0 TFB0 0 0 B1X2 0 B2X2 0 B1R2 0 B2R2 0 DX0 0 DR0 0 0 1 0 0 0C0 0 CMS 0 BP2 0 TLB 0 MOB 0 D2 0 RFS 0 0 B1X1 0 B2X1 0 B1R1 0 B2R1 0 SX1 0 SR1 0 0 0 0 0 C2E 0 BEX 0 RR 0 T15D 0 CTC 0 D1 0 LFS 0 0 B1X0 0 B2X0 0 B1R0 0 B2R0 0 SX0 0 SR0 0 0
ACTAUT PUPAUT
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Table 8: REGISTER ACCESS MESSAGES (Continued)
FUNCTION TXM4 TXM4 TXM56 TXM56 TXACT TXACT BEC1 BEC2 ECT1 ECT1 ECT2 ECT2 RXOH RESERVED TXEOC TXEOC RESERVED IDR DR FREE FREE MPWS
Notes: 1. All transmit registers can be read-back by setting bit 7 of BYTE 1 equal 1 except for TXEOC register. To read-back TXEOC, use the command 61-00 H. 2. BEC1, BEC2 and IDR are read-only registers. 3. FREE adresses are ignored by the device. 4. In the TXEOC register: E = ea1, the msb of the EOC destination address F = ea2 G = ea3 H = dm, the EOC data/message mode indicator 5. M42x is significant in NT mode only
BYTE 1 AD7/4 W R W R W R R R W R W R W W R R R 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0101 0110 0111 1000 1001 101X 11XX W 1111 AD3/1 000 000 001 001 010 010 011 100 101 101 110 110 111 111 EFG 000 XXX 000 XXX XXX XXX 111 AD0 0 1 0 1 0 1 1 1 0 1 0 1 0 0 H 1 X 0 X X X 0 7 0 0 0 0 0 0 0 0 0 0 EOC 0 0 0 0 0 0 0 6 M42x 0 0 0 0 0 0 0 0 0 M4 0 0 0 0 0 0 0 5 M43x 0 0 0 0 0 0 0 0 0 M56 0 0 0 0 0 0 0
BYTE 2 4 M44x 0 M51x 0 0 0 0 0 0 0 ACT 0 0 0 0 0 0 0 3 M45x 0 M61x 0 C4x 0 0 0 0 0 0 0 0 0 0 0 0 0 2 M46x 0 M52x 0 C3x 0 0 0 0 0
STATUS
1 0 0 FEBx 0 C2x 0 0 0 0 0 0 0 0 0 0 0 0 0
0 M48x 0 FEBx 0 C1x 0 0 0 0 0 RST 0 0 0 0 0 0 0
ECT17 ECT16 ECT15 ECT14 ECT13 ECT12 ECT11 ECT10 ECT27 ECT26 ECT25 ECT24 ECT23 ECT22 ECT21 ECT20
0 0 0 0 0 0 0
XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8
FF = Mode B
00 = Mode A
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Table 9: READ BACK MESSAGES
FUNCTION OPR CR1 CR2 CR3 CR4 CR5 CR6 TXB1 TXB2 RXB1 RXB2 TXD RXD TXM4 TXM56 TXACT BEC1 BEC2 ECT1 ECT2 TXEOC IDR BYTE 1 AD7/4 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0011 0100 0100 0100 0100 0100 0100 0100 0110 1000 AD3/1 000 001 010 011 100 101 110 000 001 010 011 100 101 000 001 010 011 100 101 110 EFG 000 1 1 1 1 1 1 1 1 1 1 1 1 1 H 0 AD0 1 1 1 1 1 1 7 CIE FF1 SFS LB1 EB1 I04 T1SE 0 0 0 0 DX5 DR5 0 0 0 c7 c7 ECT17 ECT27 0 6 EIE FF0 NTS LB2 EB2 I03
ACTUAT
BYTE 2 5 FIE CK2 DMO LBD ED I02
PUPAUT
4 OB1 CK1 DEN DB1 FFIT I01 QM B1X4 B2X4 B1R4 B2R4 DX2 DR2 M44x M51x 0 c4 c4 ECT14 ECT24 0
3 OB0 CK0 DD DB2 ESFr D4 AIS B1X3 B2X3 B1R3 B2R3 DX1 DR1 M45x M61x C4x c3 c3 ECT13 ECT23 1
2 0C1 DDM BP1 DBD CTLIO D3 TFB0 B1X2 B2X2 B1R2 B2R2 DX0 DR0 M46x M52x C3x c2 c2 ECT12 ECT22 XEOC6 0
1 0C0 CMS BP2 TLB MOB D2 RFS B1X1 B2X1 B1R1 B2R1 SX1 SR1 0 FEBx C2x c1 c1 ECT11 ECT21 0
0 C2E BEX RR T15D CTC D1 LFS B1X0 B2X0 B1R0 B2R0 SX0 SR0 M48x FEBx C1x c0 c0 ECT10 ECT20 0
0 0 0 0 DX4 DR4 M42x 0 0 c6 c6 ECT16 ECT26 0
B1X5 B2X5 B1R5 B2R5 DX3 DR3 M43x 0 0 c5 c5 ECT15 ECT25 XEOC3 0
XEOC1 XEOC2
XEOC4 XEOC5
XEOC7 XEOC8
Notes: 1. For all these registers with the exception of TXEOC, bit 0 of BYTE 1 is set to 1 to indicate read-back message. 2. CR5 configuration/status register is listed with status registers. 3. Bit 7 of BYTE 1 is the first clocked out from the UID. 4. M42x is significant in NT mode only
Table 10: SPONTANEOUS OR DRIVEN MESSAGES
FUNCTION CR5 STATUS RXM4 RXM56 RXACT BEC1 BEC2 RXEOC
Notes: 1. All status registers can be read by setting first the appropriate command. At any status change, an interrupt cycle is issued. 2. In the RXEOC register: E = ea1 F = ea2 G = ea3 H = d=0/m = 1 3. For all These registers with the exception of RXEOC, bit 0 of BYTE 1 is set to 0 to indicate a status register.
BYTE 1 AD7/4 0010 0011 0100 0100 0100 0100 0100 0101 AD3/1 101 111 000 001 010 011 100 EFG AD0 0 0 0 0 0 0 0 H 7 IO4 PWDN M41R 0 0 c7 c7 REOC1 6 IO3 0 M42R 0 0 c6 c6 REOC2 5 IO2 0 M43R 0 0 c5 c5 REOC3 4
BYTE 2 3 D4 RxFFU M45R M61R C4R c3 c3 REOC5 2 D3 RxFFO M46R M52R C3R c2 c2 REOC6 1 D2 TxFFU M47R FEBR C2R c1 c1 REOC7 0 D1 TxFFO M48R NEBR C1R c0 c0 REOC8 IO1 0 M44R M51R 0 c4 c4 REOC4
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Figure 11: Transformer Design. 6 120T 5 LINE SIDE (secondary) 8 120T 7 1.5:1 Line Interface Circuit It is very important, comply with ANSI, ETSI and French standards, that the recommended line interface circuit should be strictly adhered to. The channel response and dynamic range of this circuit have been carefully designed as an integral part of the overall signal processing system to ensure that the performance requirements are met under all the specified loop conditions. Deviations from this design are likely to result in sub-optimal performance or even total failure of the system on some types of loops. Turns Ratio: Np:Ns = 1:1.5. Secondary Inductance: Lp 27mH. Max leakage inductance: 100H Winding Resistances: 30 ohms (2.25Rp + Rs) > 10 ohms. Return Loss, at 40 kHz and load of 135 ohms: 26 dB. Saturation characteristics: THD -70dB when tested with 50mA d.c. through the secondary and a 40kHz sine-wave injected into the primary at a level which generates, at the secondary, 5VP-P (Rload = 135ohms). List of suppliers: SHOTT PULSE ENGINEERING AIE Table 11.
WINDING 1-2 6-5, 8-7 3-4 WINDING 1-2 + 3-4 5-6 + 7-8 NUMBER OF TURNS 98 Single 120+120 Bifilar 62 Single INDUCTANCE 12 mH 27 mH WIRE GAUGE #34 AWG #36 AWG #34 AWG RESISTANCE less than 5 less than 10
.. ..
1 98T 2 3 62T 4 DEVICE SIDE (primary)
Board Layout While the pins of the UID are well protected against electrical misuse, it is recommended that the standard CMOS practise, of applying GND to the device before any other connections are made, should always be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used. Great care must be taken in the layout of the printed circuit board in order to preserve the high transmission performance of the STLC5411. To maximize performance, do not use the philosophy of separating analog and digital grounds for chip. The 3 GND pins should be connected together as close as possible to the pins, and the 2 VCC pins should be strapped together. All ground connections to each device should meet at a common point as close as possible to the 3 GND pins to prevent the interaction of ground return currents flowing through a common bus impedance. Two decoupling capacitors of 10F and 0.1F should be connected from this common point to VCC pins as close as possible to the chip. Taking care with the board layout in the following ways will also help prevent noise injection into the receiver frontend and maximize the transmission performances. Keep the crystal oscillator components away from the receiver inputs and use a shielded ground plane around these components. Keep the device, the components connected to LI+/LI- and the transformer as close possible. Symmetrical layout for the line interface is suggested.
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Figure 12: Recommended connections.
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Figure 13a: LT Application.
STLC5411
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Figure 13b: NT Application.
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Figure 13c: RR Application.
STLC5411
STLC5411
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APPENDIX A - STATE MATRIX
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APPENDIX B - ELECTRICAL PARAMETERS ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN TA Tstg Supply Voltage Input Voltage Operting Temperature Range Storage TemperatureRange Parameter Value - 0.3 to 7.0 - 0.3 to 7.0 0 to 70 - 55 to 150 Unit V V C C
TRANSMISSION ELECTRICAL PARAMETERS
Parameter LINE INTERFACE FEATURES Differential Input Resistance between LI+/LI- (0-20KHz Bandwidth) Common Mode Input Resistance Power up Output Differential Impedance (0-20KHz) between LO+/LOPower Down Output Diffrential Impedance (0-20KHz) between LO+/LOPOWER CONSUMPTION ICC in Power Down ICC in Power Up Transmitting (2) TRANSMISSION PERFORMANCES Transmit Pulse Amplitude on LO+, LOTransmit Pulse Linearity (1:3 ratio accurancy) 3.27 36 50 3.61 V dB 4 70 8 80 mA mA 8 to be characterized to be characterized 1 12 5 16 K K Min. Typ. Max. Unit
(1) This specification garanties the ANSI specification, concerning the pulse amplitude using the line interface recommended schematics, of 2,5 ae 5% Volts peak amplitude for 2B1Q pulse. (2) Test condition: VDD = 5V, 2B1Q random signal transmitted with recommended 27mH line interface (fig 12) terminated with 135.
STATIC CHARACTERISTICS
Symbol VCC VIL VIH VILX VIHX VOL Parameter DC Supply Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage All Dig Inputs except XTAL1 All Dig Inputs except XTAL1 XTAL1 Input XTAL1 Input Br, IO = +7mA All other Digital Outputs, Iol = +1mA Br, IO = -7mA All other Digital Outputs IO = -1mA All Outputs (3), IO = -100A Any Digital Vin = VDD Input pin numbers: 14,15,16, 22,26,18, Vin = GND Input pin numbers: 6,7,12,13 17,19,25,27,28 Vin = GND GND < Vin < VDD LI+ and LI- to GND GND < Vout < VDD ; All Digital Outputs except XTAL2 2.4 2.4 VDD-0.5 0 -10 -100 -200 -10 10 0 0 200 10 VDD-0.5 0.4 0.4 2.2 0.5 Test Condition Min. 4.75 Typ. Max. 5.25 0.7 Unit V V V V V V V V V V A A A A A A
VOH
Output High Voltage
ILH ILL ILLR ILLX ILLI IOZ
Input Current Input Current Input Current with Internal Pull Up Resistor Input Current on XTAL1 Input Current on LI+/LIOutput Current in High Impedance State (TRISTATE)
to be characterized
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TIMING CHARACTERISTICS
Symbol Parameter Frequency of MCLK Tolerance MCLK/XTAL Input Clock Jitter tWMH tWML tRM tFM FBCLK tWBH tWBL tRB tFB tSFB tHBF tDBF tDBD tDBDZ tDFD tSDB tHBD tDBT tDBTZ tDFT tSDD tHDD tDDD FCCLK tWCH tWCL tRC tFC tSSC tHCS tWSH tSIC tHCI tDSO tDCO tDCOZ tDCI Clock Pulse Width, MCLK High Level Clock Pulse Width, MCLK Low Level Rise Time of MCLK Fall Time of MCLK Frequency of BCLK Clock Pulse Width, BCLK High Level Clock Pulse Width, BCLK Low Level Risae Time of BCLK Fall Time of BCLK Setup Time, FS High or Low to BCLK Low Hold Time, BCLK Low to FS High or Low Delay Time, BCLK High to FS High or Low Delay Time, BCLK High to Data Valid Delay Time, BCLK High to Data HZ Delay Time, FS High to Data Valid Setup Time, Data Valid to BCLK Low Hold time, BCLK to Data Invalid Delay Time, BCLK High to TSR Low Delay Time, BCLK Low to TSR HZ Delay Tie, FS High to TSR Low Setup Time, DCLK Low to DX High or Low Hold Time, DCLK Low to DX High or Low Delay Time, DCLK High to DR High or Low Frequency of CCLK Clock Pulse Width, CCLK High Level Clock Pulse Width, CCLK Low Level Rise Time of CCLK Fall Time of CCLK Setup Time, CSB Low to CCLK High Hold Time, CCLK Low to CSB High Duration of CSB High Setup Time, CI Valid to CCLK High Hold Time, CCLK High to CI Invalid Delay Time, CSB Low to CO Valid Delay Time CCLK Low to CO Valid Delay Time, CCLK Low to CO HZ Delay Time, CCLK Low to INTB Low or HZ Load = 80pF + 2LSTTL Loads Out First Bit on CO Load = 50 pF + 2LSTTL Loads Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 60 10 200 25 25 50 50 50 50 85 85 15 15 Load = 50pF + 2 LSTTL Loads Load = 100pF + 2 LSTTL Loads 50 50 80 5 Load = 100pF + 2 LSTTL Loads Load = 150pF + 2 LSTTL Loads 0 20 80 50 80 Test Condition Including Temperature, Aging, Etc... External Clock Source VIH = VCC - 0.5V VIL = 0.5V Used as a Logic Input 20 20 10 10 256 512 30 30 15 15 30 20 -20 20 80 50 80 4095 6144 Min. Typ. 15.36 -100 +100 50 Max. Unit MHz ppm ns pk-pk ns ns ns ns KHz KHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
MASTER CLOCK
FMCLK
DIGITAL INTERFACE
Formats 1, 2 and 3 Format 4 and GCI Mode Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL DSI or GCI Slave Mode only DSI or GCI Slave Mode only DSI or GCI Master Mode only Load = 150pF + 2 LSTTLLoads ( *
D PORT IN CONTINUOUS MODE: 16KBITS/SEC
MICROWIRE CONTROL INTERFACE
(* In GCI mode: Load Res.
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Figure 14: BCLK, FSA, FSB, SLAVE MODE, DELAYED MODE, FORMATS 1 2 3 (MW ONLY).
Figure 15: BCLK, FSA, FSB, SLAVE MODE, NON DELAYED MODE, FORMATS 1 2 3 (MW ONLY).
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Figure 16: BCLK, FSA, FSB, SLAVE MODE, FORMAT 4 ALWAYS NON DELAYED MODE, (MW AND GCI MODE).
Figure 17: BCLK, FSA, FSB, MASTER MODE, DELAYED MODE, FORMATS 1 2 3 (MW ONLY).
tFB
Note 1 t RB Note 1 Note 1
BCLK
OUTPUT
tDBF tDBF FSA
OUTPUT
tDBF tDBF
tDBF tDBF FSB
OUTPUT
tDBF tDBF
BX
INPUT
or
BR
OUTPUT
LAST BIT OF THE FRAME
FIRST BIT OF THE FRAME
SECOND BIT SEVENTH BIT OF THE OF THE FRAME FRAME
EIGHT BIT OF THE FRAME
D96TL253
Note 1: in accordance to the selected frequency. High level duration - Low level duration
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Figure 18: BCLK, FSA, FSB, MASTER MODE, NON DELAYED MODE, FORMATS 1 3 (MW ONLY).
Figure 19: BCLK, FSA, FSB, MASTER MODE, FORMAT 4 ALWAYS NON DELAYED MODE, (MW AND GCI MODE).
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Figure 20: BX, DX, BR, DR, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS 1 2 3 (MW ONLY)
Figure 21: BX, DX, BR, DR, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED, (MW & GCI MODE)
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Figure 22: SPECIAL CASE BR, DR, ONLY FIRST BIT OF THE FRAME, IN SLAVE AND NON DELAYED MODES FORMATS 1 3 (MW MODE), FORMAT 4 (MW & GCI MODE)
Figure 23: TSRB, SLAVE & MASTER, DELAYED & NON DELAYED, FORMATS 1 2 3 (MW ONLY)
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Figure 24: TSRB, SLAVE & MASTER, FORMAT 4 ALWAYS NON DELAYED MODE (MW & GCI)
Figure 25: SPECIAL CASE TSRB, B1 OR B2 FIRST CHANNEL OF THE FRAME, IN SLAVE & NON DELAYED MODE, FORMATS 1 3 (MW MODE), FORMAT 4 (MW & GCI MODE)
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Figure 26: DCLK, DX, DR IN CONTINUOUS MODE SLAVE & MASTER, DELAYED & NON DELAYED MODES ALL FORMATS IN MW MODE ONLY
Figure 24: MCLK ALL MODES
Figure 25: MW PORT Mode A
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Figure 26: MW PORT Mode B
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PLCC44 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D d1 d2 E e e3 F F1 G M M1 1.16 1.14 14.99 1.27 12.7 0.46 0.71 0.101 0.046 0.045 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.018 0.028 0.004 mm TYP. MAX. 17.65 16.65 3.7 4.57 2.74 MIN. 0.685 0.650 0.144 0.165 0.102 0.027 0.630 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108
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DIP28 PLASTIC PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.130 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Swit zerland - Taiwan - Thailand - United Kingdom - U.S.A.
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